Rabindra K. Roy

According to our database, Rabindra K. Roy authored at least 39 papers between 1988 and 2000.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2000

EDA challenges facing future microprocessor design.

T. Karn, Shishpal Rawat, Desmond Kirkpatrick, Rabindra K. Roy, Gregory S. Spirakis, Naveed A. Sherwani, Craig Peterson

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1999

Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits.

Huy Nguyen, Rabindra K. Roy, Abhijit Chatterjee

J. Electron. Test., 1999

Characterizing Individual Gate Power Sensitivity in Low Power Design.

Unni Narayanan, Georgios I. Stamoulis, Rabindra K. Roy

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1998

Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis.

Huy T. Nguyen, Abhijit Chatterjee, Rabindra K. Roy

J. VLSI Signal Process., 1998

Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits.

Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey

J. Electron. Test., 1998

Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential Circuits.

Huy Nguyen, Rabindra K. Roy, Abhijit Chatterjee

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Considering Testability during High-level Design (Embedded Tutorial).

Sujit Dey, Anand Raghunathan, Rabindra K. Roy

Proceedings of the ASP-DAC '98, 1998

1997

Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization.

Abhijit Chatterjee, Rabindra K. Roy

IEEE Trans. Computers, 1997

T5: Low-Power Design.

Kaushik Roy, Rabindra K. Roy, Ramesh Harjani, K. S. Murthy

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Impact of Partial Reset on Fault Independent Testing and BIST.

Huy Nguyen, Abhijit Chatterjee, Rabindra K. Roy

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

Synthesis of initializable asynchronous circuits.

Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan

IEEE Trans. Very Large Scale Integr. Syst., 1996

Initialization issues in asynchronous circuit synthesis.

Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar

J. Electron. Test., 1996

Synchronous Test Generation Model for Asynchronous Circuits.

Savita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995

Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan.

Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints.

Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Guest Editors' Introduction: More Practical Asynchronous Design.

Tam-Anh Chu, Rabindra K. Roy

IEEE Des. Test Comput., 1995

Advantages of High-Level Test Synthesis over Design for Test.

Rabindra K. Roy

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Synthesis-for-testability using transformations.

Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

Guest Editor's Introduction: Practical Asynchronous Design.

Tam-Anh Chu, Rabindra K. Roy

IEEE Des. Test Comput., 1994

Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application.

Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Design for diagnosability of linear digital filters using time-space expansion.

Abhijit Chatterjee, Rabindra K. Roy

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Synthesis of Low Power Linear DSP Circuits Using Activity Metrics.

Abhijit Chatterjee, Rabindra K. Roy

Proceedings of the Seventh International Conference on VLSI Design, 1994

Initialization Isuues in the Synthesis of Asynchronous Circuits.

Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Behavioral synthesis of low-cost partial scan designs for DSP applications.

Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy

Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994

Signal Transition Graph Transformations for Initializability.

Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Greedy hardware optimization for linear digital circuits using number splitting and refactorization.

Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu

IEEE Trans. Very Large Scale Integr. Syst., 1993

Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting.

Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu

Proceedings of the Sixth International Conference on VLSI Design, 1993

Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters.

Abhijit Chatterjee, Rabindra K. Roy

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Exploiting hardware sharing in high-level synthesis for partial scan optimization.

Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition.

Abhijit Chatterjee, Rabindra K. Roy

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Test compaction for sequential circuits.

Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Dynamic redundancy identification in automatic test generation.

Miron Abramovici, David T. Miller, Rabindra K. Roy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Delay fault testing of iterative arithmetic arrays.

Rabindra K. Roy, Naveena Nagi, Abhijit Chatterjee, Manuel A. d'Abreu

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Automatic test generation for linear digital systems with bi-level search using matrix transform methods.

Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991

Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors.

Abhijit Chatterjee, Rabindra K. Roy, Jacob A. Abraham, Janak H. Patel

Digit. Signal Process., 1991

The Best Flip-Flops to Scan.

Miron Abramovici, James J. Kulikowski, Rabindra K. Roy

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

Timing verification and synthesis of circuits for delay fault testability

Rabindra K. Roy

PhD thesis, 1990

1988

Compaction of ATPG-generated test sequences for sequential circuits.

Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Fault Simulation in a Distributed Environment.

Patrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988