R. G. Raghavendra

According to our database, R. G. Raghavendra authored at least 4 papers between 2005 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2016

A 1-tap 10.3125Gb/s Programmable Voltage Mode Line Driver in 28nm CMOS Technology.

R. G. Raghavendra, Balbeer Singh Rathor

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2007

Area efficient loop filter design for charge pump phase locked loop.

R. G. Raghavendra, Bharadwaj Amrutur

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

An On-Chip Voltage Regulator with Improved Load Regulation and Light Load Power Efficiency.

R. G. Raghavendra, Pradip Mandal

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005

On-Chip Voltage Regulator with Improved Transient Response.

Ashis Maity, R. G. Raghavendra, Pradip Mandal

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005