R. Franiatte

According to our database, R. Franiatte authored at least 4 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Hybrid Integration of 3D-RF Interconnects on AlGaN/GaN/Si HEMT RF Transistor featuring 2.2W/mm Psat & 41% PAE @28GHz using a Robust and Cost-Effective Chiplet Heterogeneous Bonding Technique.

A. Divay, O. Valorge, C. Dubarry, M. Medbouhi, R. Franiatte, D. Mermin, R. Velard, Y. Gobil, F. Morisot, Erwan Morvan, Ismael Charlet, Luca Lucci, J. Lugo, Xavier Garros

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2016

Heat spreading packaging solutions for hybrid bonded 3D-ICs.

Rafael Prieto, Perceval Coudrain, Jean-Philippe Colonna, Y. Hallez, Christian Chancel, Venceslass Rat, Sylvain Dumas, G. Romano, R. Franiatte, C. Brunet-Manquiat, Séverine Cheramy, Alexis Farcy

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015

Silicon based dry-films evaluation for 2.5D and 3D Wafer-Level system integration improvement.

Amadine Jouve, Y. Sinquin, Arnaud Garnier, M. Daval, Pascal Chausse, M. Argoud, N. Allouti, Laurence Baud, Jérôme Dechamp, R. Franiatte, Séverine Cheramy, H. Kato, K. Kondo

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2013

Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integration.

Sylvain Joblot, Alexis Farcy, Nicolas Hotellier, Amadine Jouve, François de Crecy, Arnaud Garnier, M. Argoud, C. Ferrandon, J.-P. Colonna, R. Franiatte, C. Laviron, Séverine Cheramy

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013