R. D. (Shawn) Blanton

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Faulty Function Extraction for Defective Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2024

Silent Data Corruption: Test or Reliability Problem?

[BibT_eX]

[DOI]

Erik Jan Marinissen

Harish Dattatraya Dixit

Proceedings of the IEEE European Test Symposium, 2024

2023

Efficient Test Chip Design via Smart Computation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., March, 2023

Characterize the ability of GNNs in attacking logic locking.

[BibT_eX]

[DOI]

Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Global Floorplanning via Semidefinite Programming.

[BibT_eX]

[DOI]

Wei Li

Fangzhou Wang

José M. F. Moura

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

PEPR: Pseudo-Exhaustive Physically-Aware Region Testing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2022

Large-Scale Logic-Locking Attacks via Simulation.

[BibT_eX]

[DOI]

Ruben Purdy

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Secuirty Metrics for Logic Circuits.

[BibT_eX]

[DOI]

Ruben Purdy

Danielle Duvalsaint

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

2021

Split-Chip Design to Prevent IP Reverse Engineering.

[BibT_eX]

[DOI]

IEEE Des. Test, 2021

Memory-Efficient Adaptive Test Pattern Reordering for Accurate Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

AAA: Automated, On-ATE AI Debug of Scan Chain Failures.

[BibT_eX]

[DOI]

Chris Nigh

Gaurav Bhargava

Proceedings of the IEEE International Test Conference, 2021

Characterizing Corruptibility of Logic Locks using ATPG.

[BibT_eX]

[DOI]

Danielle Duvalsaint

Proceedings of the IEEE International Test Conference, 2021

2020

Towards Smarter Diagnosis: A Learning-based Diagnostic Outcome Previewer.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2020

Partial Bayesian Co-training for Virtual Metrology.

[BibT_eX]

[DOI]

Cuong Manh Nguyen

Ronald DeShawn Blanton

Xiang Li

IEEE Trans. Ind. Informatics, 2020

CircuitGraph: A Python package for Boolean circuits.

[BibT_eX]

[DOI]

J. Open Source Softw., 2020

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.

[BibT_eX]

[DOI]

CoRR, 2020

A Deterministic-Statistical Multiple-Defect Diagnosis Methodology.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Special Session: Novel Attacks on Logic-Locking.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Knowledge Transfer for Diagnosis Outcome Preview with Limited Data.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

Diagnosis Outcome Prediction on Limited Data via Transferred Random Forest.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2020

Adaptive Test Pattern Reordering for Diagnosis using k-Nearest Neighbors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2020

Design Obfuscation versus Test.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2020

Efficient Classification via Partial Co-Training for Virtual Metrology.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Emerging Technologies and Factory Automation, 2020

DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY.

[BibT_eX]

[DOI]

Benjamin Carrión Schäfer

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

IC Protection Against JTAG-Based Attacks.

[BibT_eX]

[DOI]

Francisco Pimentel Torres

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

On-Chip Diagnosis of Generalized Delay Failures Using Compact Fault Dictionaries.

[BibT_eX]

[DOI]

Matthew Layne Beckler

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Path Delay Test of the Carnegie Mellon Logic Characterization Vehicle.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Diagnosis Outcome Preview through Learning.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Improving Test Chip Design Efficiency via Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2019

Characterization of Locked Combinational Circuits via ATPG.

[BibT_eX]

[DOI]

Danielle Duvalsaint

Xiaoxiao Jin

Benjamin Niewenhuis

Proceedings of the IEEE International Test Conference, 2019

Characterization of Locked Sequential Circuits via ATPG.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

LearnX: A Hybrid Deterministic-Statistical Defect Diagnosis Methodology.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE European Test Symposium, 2019

FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs.

[BibT_eX]

[DOI]

Ruizhou Ding

Diana Marculescu

ACM Trans. Reconfigurable Technol. Syst., 2018

Improving Diagnostic Resolution of Failing ICs Through Learning.

[BibT_eX]

[DOI]

Yang Xue

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

NOIDA: Noise-resistant Intra-cell Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Improving Diagnosis Efficiency via Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

Back-End Layout Reflection for Test Chip Design.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Detection of IJTAG attacks using LDPC-based feature reduction and machine learning.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE European Test Symposium, 2018

CompactNet: High Accuracy Deep Neural Network Optimized for On-Chip Implementation.

[BibT_eX]

[DOI]

Abhinav Goel

Proceedings of the IEEE International Conference on Big Data (IEEE BigData 2018), 2018

Quantized deep neural networks for energy efficient hardware-based inference.

[BibT_eX]

[DOI]

Ruizhou Ding

Diana Marculescu

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

DFM Evaluation Using IC Diagnosis Data.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Test-set reordering for improving diagnosability.

[BibT_eX]

[DOI]

Cheng Xue

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Front-end layout reflection for test chip design.

[BibT_eX]

[DOI]

Phillip Fynan

Proceedings of the IEEE International Test Conference, 2017

Fault simulation acceleration for TRAX dictionary construction using GPUs.

[BibT_eX]

[DOI]

Matthew Beckler

Proceedings of the IEEE International Test Conference, 2017

GPU-accelerated fault dictionary generation for the TRAX fault model.

[BibT_eX]

[DOI]

Matthew Beckler

Proceedings of the International Test Conference in Asia, 2017

Random Forest Architectures on FPGA for Multiple Applications.

[BibT_eX]

[DOI]

Xiang Lin

Donald E. Thomas

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Multiple-defect diagnosis for Logic Characterization Vehicles.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE European Test Symposium, 2017

Partial co-training for virtual metrology.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Emerging Technologies and Factory Automation, 2017

PADLOC: Physically-Aware Defect Localization and Characterization.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Ensemble Reduction via Logic Minimization.

[BibT_eX]

[DOI]

Hongfei Wang

ACM Trans. Design Autom. Electr. Syst., 2016

Test: Wisdom From the Giants, Visions for the Future - Part 2.

[BibT_eX]

[DOI]

David Yeh

IEEE Des. Test, 2016

Test chip design for optimal cell-aware diagnosability.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

Diagnostic resolution improvement through learning-guided physical failure analysis.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

Logic characterization vehicle design reflection via layout rewiring.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

A Learning-Based Approach to Secure JTAG Against Unseen Scan-Based Attacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Achieving 100% cell-aware coverage by design.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

LASIC: Layout Analysis for Systematic IC-Defect Identification Using Clustering.

[BibT_eX]

[DOI]

Wing Chiu Jason Tam

Ronald Shawn Blanton

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Improving accuracy of on-chip diagnosis via incremental learning.

[BibT_eX]

[DOI]

Mitchell Martin

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Efficient built-in self test of regular logic characterization vehicles.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Special session: Hot topics: Statistical test methods.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Design reflection for optimal test-chip implementation.

[BibT_eX]

[DOI]

Benjamin Niewenhuis

Zeye (Dexter) Liu

Proceedings of the 2015 IEEE International Test Conference, 2015

A one-pass test-selection method for maximizing test coverage.

[BibT_eX]

[DOI]

Cheng Xue

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Statistical Learning in Chip (SLIC).

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Detection of illegitimate access to JTAG via statistical learning in chip.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis.

[BibT_eX]

[DOI]

Hongfei Wang

ACM Trans. Design Autom. Electr. Syst., 2014

Design-for-Manufacturability Assessment for Integrated Circuits Using RADAR.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling.

[BibT_eX]

[DOI]

Shanghang Zhang

José Machado da Silva

John M. Carulli Jr.

Kenneth M. Butler

Proceedings of the 2014 International Test Conference, 2014

Logic characterization vehicle design for maximal information extraction for yield learning.

[BibT_eX]

[DOI]

Carl Taylor

Proceedings of the 2014 International Test Conference, 2014

SLIC: Statistical learning in chip.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Ultra-low-power biomedical circuit design and optimization: Catching the don't cares.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Predicting IC Defect Level Using Diagnosis.

[BibT_eX]

[DOI]

Cheng Xue

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Physically-Aware Diagnostic Resolution.

[BibT_eX]

[DOI]

John A. Porche

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Special session 4B: Elevator talks.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

PADRE: Physically-Aware Diagnostic Resolution Enhancement.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

DREAMS: DFM rule EvAluation using manufactured silicon.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012

Improving Diagnosis Through Failing Behavior Identification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Diagnosis-Assisted Adaptive Test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

SLIDER: Simulation of Layout-Injected Defects for Electrical Responses.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Physically-Aware N-Detect Test.

[BibT_eX]

[DOI]

Phil Nigh

Peter Lloyd

Vikram Iyengar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Physically-Aware Analysis of Systematic Defects in Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2012

Yield Learning Through Physically Aware Diagnosis of IC-Failure Populations.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2012

On-chip diagnosis for early-life and wear-out failures.

[BibT_eX]

[DOI]

Matthew Beckler

Proceedings of the 2012 IEEE International Test Conference, 2012

Test-data volume optimization for diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

METER: Measuring Test Effectiveness Regionally.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Reducing Test Execution Cost of Integrated, Heterogeneous Systems Using Continuous Test Data.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

SLIDER: A fast and accurate defect simulation framework.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Statistical defect-detection analysis of test sets using readily-available tester data.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

To DFM or not to DFM?

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

Diagnosis of Integrated Circuits With Multiple Defects of Arbitrary Characteristics.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Enhancing CMOS Using Nanoelectronic Devices: A Perspective on Hybrid Integrated Systems.

[BibT_eX]

[DOI]

Proc. IEEE, 2010

Evaluating yield and testing impact of sub-wavelength lithography.

[BibT_eX]

[DOI]

Wojciech Maly

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Estimating defect-type distributions through volume diagnosis and defect behavior attribution.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Systematic defect identification through layout snippet clustering.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Automatic classification of bridge defects.

[BibT_eX]

[DOI]

Jeffrey E. Nelson

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

Controlling DPPM through Volume Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Physically-Aware N-Detect Test Relaxation.

[BibT_eX]

[DOI]

Chukwuemeka U. Ezekwe

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Maintaining Accuracy of Test Compaction through Adaptive Re-learning.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Test effectiveness evaluation through analysis of readily-available tester data.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits.

[BibT_eX]

[DOI]

Rob A. Rutenbar

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Automated failure population creation for validating integrated circuit diagnosis methods.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

An Effective and Flexible Multiple Defect Diagnosis Methodology Using Error Propagation Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Improving the Accuracy of Test Compaction through Adaptive Test Update.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Automated Standard Cell Library Analysis for Improved Defect Modeling.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Physically-Aware N-Detect Test Pattern Selection.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Automated Testability Enhancements for Logic Brick Libraries.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Multiple defect diagnosis using no assumptions on failing pattern characteristics.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Precise failure localization using automated layout analysis of diagnosis candidates.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology.

[BibT_eX]

[DOI]

J. Electron. Test., 2007

Delay defect diagnosis using segment network faults.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

2006

Inductive fault analysis of surface-micromachined MEMS.

[BibT_eX]

[DOI]

Tao Jiang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Defect Modeling Using Fault Tuples.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Extracting Defect Density and Size Distributions from Product ICs.

[BibT_eX]

[DOI]

Wojciech Maly

Brady Benware

Chris Schuermyer

IEEE Des. Test Comput., 2006

Statistical Test Compaction Using Binary Decision Trees.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2006

Exploiting Regularity for Inductive Fault Analysis.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

Diagnostic Test Generation for Arbitrary Faults.

[BibT_eX]

[DOI]

Naresh K. Bhatti

Proceedings of the 2006 IEEE International Test Conference, 2006

Extraction of defect density and size distributions from wafer sort test results.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Multiple-detect ATPG based on physical neighborhoods.

[BibT_eX]

[DOI]

Jeffrey E. Nelson

Proceedings of the 43rd Design Automation Conference, 2006

2005

Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead.

[BibT_eX]

[DOI]

Subhasish Mitra

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Specification Test Compaction for Analog Circuits and MEMS.

[BibT_eX]

[DOI]

Peng Li

Larry T. Pileggi

Proceedings of the 2005 Design, 2005

2004

Multi-Modal Built-In Self-Test for Symmetric Microsystems.

[BibT_eX]

[DOI]

Nilmoni Deb

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Generalized Sensitization using Fault Tuples.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations.

[BibT_eX]

[DOI]

Thomas J. Vogels

Thomas Zanon

Padmini Gopalakrishnan

Mahim Mishra

Vyacheslav Rovner

S. Tiwary

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

CAEN-BIST: Testing the NanoFabric.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST.

[BibT_eX]

[DOI]

Chunsheng Liu

Krishnendu Chakrabarty

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

2003

On the properties of the input pattern fault model.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2003

Progressive Bridge Identification.

[BibT_eX]

[DOI]

Thomas J. Vogels

Wojciech Maly

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Deformations of IC Structure in Test and Yield Learning.

[BibT_eX]

[DOI]

Thomas M. Storey

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Analyzing the Effectiveness of Multiple-Detect Test Sets.

[BibT_eX]

[DOI]

Anirudh B. Shah

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

ATPG for Noise-Induced Switch Failures in Domino Logic.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002

Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation.

[BibT_eX]

[DOI]

Ravishankar Arunachalam

Ronald DeShawn Blanton

Lawrence T. Pileggi

VLSI Design, 2002

Test vector generation for charge sharing failures in dynamic logic.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Modeling the Economics of Testing: A DFT Perspective.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2002

SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow?

[BibT_eX]

[DOI]

Salvador Mir

H. Bederr

Hans G. Kerkhoff

H. J. Klim

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Exploiting Dominance and Equivalence using Fault Tuples.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Built-In Self Test of CMOS-MEMS Accelerometers.

[BibT_eX]

[DOI]

Nilmoni Deb

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Fault Tuples in Diagnosis of Deep-Submicron Circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Testing of Dynamic Logic Circuits Based on Charge Sharing.

[BibT_eX]

[DOI]

Keerthi Heragu

Manish Sharma

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Designing and Implementing Efficient BISR Techniques for Embedded RAMs.

[BibT_eX]

Proceedings of the 2nd Latin American Test Workshop, 2001

Relating buffer-oriented microarchitecture validation to high-level pipeline functionality.

[BibT_eX]

[DOI]

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

False Coupling Interactions in Static Timing Analysis.

[BibT_eX]

[DOI]

Ravishankar Arunachalam

Lawrence T. Pileggi

Proceedings of the 38th Design Automation Conference, 2001

2000

On the design of fast, easily testable ALU's.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

A Buffer-Oriented Methodology for Microarchitecture Validation.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

Effectiveness of Microarchitecture Test Program Generation.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2000

Identification of crosstalk switch failures in domino CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Universal test generation using fault tuples.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Analysis of failure sources in surface-micromachined MEMS.

[BibT_eX]

[DOI]

Nilmoni Deb

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Universal fault simulation using fault tuples.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

An integrated functional performance simulator.

[BibT_eX]

[DOI]

Candice Bechem

Jonathan Combs

Bryan Black

IEEE Micro, 1999

Hierarchical Design and Test of Integrated Microsystems.

[BibT_eX]

[DOI]

Tamal Mukherjee

Gary K. Fedder

IEEE Des. Test Comput., 1999

Guest Editors' Introduction.

[BibT_eX]

Bernard Courtois

IEEE Des. Test Comput., 1999

Superscalar Processor Validation at the Microarchitecture Level.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

IDDQ-Testability of Tree Circuits.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Particulate failures for surface-micromachined MEMS.

[BibT_eX]

[DOI]

Tao Jiang

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

Testing MEMS.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

MEMS fault model generation using CARAMEL.

[BibT_eX]

[DOI]

Abhijeet Kolpekwar

Chris S. Kellen

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Failure modes for stiction in surface-micromachined MEMS.

[BibT_eX]

[DOI]

Abhijeet Kolpekwar

David Woodilla

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Using regression analysis for GA-based ATPG parameter optimization.

[BibT_eX]

[DOI]

William E. Dougherty

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997

Testability Properties of Divergent Trees.

[BibT_eX]

[DOI]

J. Electron. Test., 1997

To DFT or Not to DFT?

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Development of a MEMS Testing Methodology.

[BibT_eX]

[DOI]

Abhijeet Kolpekwar

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

The input pattern fault model and its application.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

1996

Testability of Convergent Tree Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1996

Design of a fast, easily testable ALU.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Synthesis of Self-Testing Finite State Machines from High-Level Specifications.

[BibT_eX]

[DOI]

Vishwani D. Agrawal

Maurizio Damiani

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995

Design and testing of regular circuits.

[BibT_eX]

[DOI]

PhD thesis, 1995

1993

Efficient Testing of Tree Circuits.

[BibT_eX]

[DOI]