R. Castagnetti

According to our database, R. Castagnetti authored at least 5 papers between 2001 and 2009.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2009

Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design.

R. Venkatraman, R. Castagnetti, Andres Teene, Benjamin Mbouombouo, S. Ramesh

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2006

The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability.

R. Venkatraman, R. Castagnetti, S. Ramesh

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005

A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC.

R. Castagnetti, R. Venkatraman, Brandon Bartz, Carl Monzel, T. Briscoe, Andres Teene, S. Ramesh

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2003

Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability.

F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2001

Substrate Engineering to Improve Soft-Error-Rate Immunity for SRAM Technologies.

Helmut Puchner, Y.-C. Liu, W. Kong, F. Duan, R. Castagnetti

Microelectron. Reliab., 2001