Qiongna Zhang

According to our database, Qiongna Zhang authored at least 3 papers between 2014 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS.

Jan Mulder, Davide Vecchi, Yi Ke, Stefano Bozzola, Mark Core, Nitz Saputra, Qiongna Zhang, Jeff Riley, Han Yan, Mattia Introini, Sijia Wang, Christopher M. Ward, Jan R. Westra, Jiansong Wan, Klaas Bult

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS.

Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers.

Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014