Qingsheng Hu

According to our database1, Qingsheng Hu authored at least 19 papers between 1999 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A COM Based High Speed Serial Link Optimization Using Machine Learning.
IEICE Trans. Electron., November, 2022

Quantum Cryptography Technology and Application in Smart Grid.
Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

Delay Optimization of Power Internet of Things based on Edge-Cloud Collaboration.
Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

2020
DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane.
IEICE Trans. Electron., 2020

2019
An Effective Differential Power Attack Method for Advanced Encryption Standard.
Proceedings of the 2019 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2019

2018
A 33 Gb/s combined adaptive CTLE and half-rate look-ahead DFE in 0.13 µm BiCMOS technology for serial link.
IEICE Electron. Express, 2018

Two Improved Algorithms for Layered QC-LDPC Decoding Algorithm.
Proceedings of the 2018 IEEE Canadian Conference on Electrical & Computer Engineering, 2018

A 40 Gb/s PAM4 SerDes Receiver in 65nm CMOS Technology.
Proceedings of the 2018 IEEE Canadian Conference on Electrical & Computer Engineering, 2018

2017
A 20 Gb/s Wireline Receiver with Adaptive CTLE and Half-Rate DFE in 0.13 µm Technology.
Proceedings of the Wired/Wireless Internet Communications, 2017

IBIS-AMI Based PAM4 Signaling and FEC Technique for 25 Gb/s Serial Link.
Proceedings of the Wired/Wireless Internet Communications, 2017

2015
PPI网络的改进马尔科夫聚类算法 (Improved MCL Clustering Algorithm in PPI Networks).
计算机科学, 2015

2014
A 6.25Gb/s feed-forward equaliser in 0.18μm CMOS using delay locked loop with load calibration.
Proceedings of the 9th International Symposium on Communication Systems, 2014

2012
A high-speed and low-power up/down counter in 0.18-μm CMOS technology.
Proceedings of the International Conference on Wireless Communications and Signal Processing, 2012

2011
High-performance FPGA implementation of packet reordering for multiple TCP connections.
Proceedings of the 11th International Symposium on Communications and Information Technologies, 2011

2010
Design and Implementation of High-Speed Input-Queued Switches Based on a Fair Scheduling Algorithm.
IEICE Trans. Electron., 2010

2008
A Programmable Frequency Divider in 0.18µm CMOS Library.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2005
Low complexity parallel Chien search architecture for RS decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
Stable and Practical Scheduling Algorithms for High Speed Virtual Output Queuing Switches.
Proceedings of the Eighth IEEE Symposium on Computers and Communications (ISCC 2003), 30 June, 2003

1999
A distributed algorithm for multi-region problem in BEM.
J. Comput. Sci. Technol., 1999


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