Qingfeng Zhuge

计算机科学, 2016

Write reconstruction for write throughput improvement on MLC PCM based main memory.

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[DOI]

J. Syst. Archit., 2016

A unified framework for designing high performance in-memory and hybrid memory file systems.

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[DOI]

J. Syst. Archit., 2016

A Convex Optimization Based Autonomous Intersection Control Strategy in Vehicular Cyber-Physical Systems.

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[DOI]

Victor Chung Sing Lee

Sang Hyuk Son

Proceedings of the 2016 Intl IEEE Conferences on Ubiquitous Intelligence & Computing, 2016

Performance Optimization for In-Memory File Systems on NUMA Machines.

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[DOI]

Proceedings of the 17th International Conference on Parallel and Distributed Computing, 2016

The design and implementation of an efficient user-space in-memory file system.

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[DOI]

Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

Towards Real-Time and Temporal Information Services in Vehicular Networks via Multi-Objective Optimization.

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[DOI]

Victor Chung Sing Lee

Sang Hyuk Son

Proceedings of the 41st IEEE Conference on Local Computer Networks, 2016

Optimizing Data Placement of MapReduce on Ceph-Based Framework under Load-Balancing Constraint.

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[DOI]

Proceedings of the 22nd IEEE International Conference on Parallel and Distributed Systems, 2016

Optimal Functional Assignment and Communication Selection under Timing Constraint for Self-Timed Pipelines.

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[DOI]

Proceedings of the 13th International Conference on Embedded Software and Systems, 2016

The Design and Implementation of an Efficient Data Consistency Mechanism for In-Memory File Systems.

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[DOI]

Proceedings of the 13th International Conference on Embedded Software and Systems, 2016

Access Characteristic Guided Read and Write Cost Regulation for Performance Improvement on Flash Memory.

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[DOI]

Proceedings of the 14th USENIX Conference on File and Storage Technologies, 2016

The design of an efficient swap mechanism for hybrid DRAM-NVM systems.

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[DOI]

Proceedings of the 2016 International Conference on Embedded Software, 2016

Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM.

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[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Optimal functional-unit assignment and buffer placement for probabilistic pipelines.

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[DOI]

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

The Design and Implementation of a High-Performance Hybrid Memory File System.

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[DOI]

Proceedings of the International Conference on Advanced Cloud and Big Data, 2016

Peak-to-average pumping efficiency improvement for charge pump in Phase Change Memories.

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[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Reliability-Guaranteed Task Assignment and Scheduling for Heterogeneous Multiprocessors Considering Timing Constraint.

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[DOI]

J. Signal Process. Syst., 2015

Low Overhead Software Wear Leveling for Hybrid PCM + DRAM Main Memory on Embedded Systems.

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[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Optimizing Task and Data Assignment on Multi-Core Systems with Multi-Port SPMs.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2015

Power Efficiency for Hardware/Software Partitioning with Time and Area Constraints on MPSoC.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2015

Designing an efficient persistent in-memory file system.

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[DOI]

Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Improving MLC PCM write throughput by write reconstruction.

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[DOI]

Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Vehicle Assisted Data Update for Temporal Information Service in Vehicular Networks.

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[DOI]

Proceedings of the IEEE 18th International Conference on Intelligent Transportation Systems, 2015

Efficient Scheduling with Intensive In-Memory File Accesses Considering Bandwidth Constraint on Memory Bus.

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[DOI]

Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

Prevent Deadlock and Remove Blocking for Self-Timed Systems.

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[DOI]

Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

On the Design of High-Performance and Energy-Efficient Probabilistic Self-Timed Systems.

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[DOI]

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Realistic Task Parallelization of the H.264 Decoding Algorithm for Multiprocessors.

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[DOI]

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

User Experience Enhanced Task Scheduling and Processor Frequency Scaling for Energy-Sensitive Mobile Devices.

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[DOI]

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

<i>n</i>Code: limiting harmful writes to emerging mobile NVRAM through code swapping.

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[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Maximizing IO performance via conflict reduction for flash memory storage systems.

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[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Area and performance co-optimization for domain wall memory in application-specific embedded systems.

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[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Optimizing data placement for reducing shift operations on domain wall memories.

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[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Minimizing System Cost with Efficient Task Assignment on Heterogeneous Multicore Processors Considering Time Constraint.

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[DOI]

IEEE Trans. Parallel Distributed Syst., 2014

Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors.

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[DOI]

ACM Trans. Embed. Comput. Syst., 2014

Application-Specific Wear Leveling for Extending Lifetime of Phase Change Memory in Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Scheduling to Optimize Cache Utilization for Non-Volatile Main Memories.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

A space allocation and reuse strategy for PCM-based embedded systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 2014

A Partition-based Mechanism for Reducing Energy in Phase Change Memory.

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[DOI]

J. Comput., 2014

Optimizing Data Distribution for Loops on Embedded Multicore with Scratch-Pad Memory.

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[DOI]

J. Comput., 2014

Efficient fault-tolerant scheduling on multiprocessor systems via replication and deallocation.

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[DOI]

Int. J. Embed. Syst., 2014

Efficient grouping-based mapping and scheduling on heterogeneous cluster architectures.

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[DOI]

Comput. Electr. Eng., 2014

Contention-aware task and communication co-scheduling for network-on-chip based Multiprocessor System-on-Chip.

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[DOI]

Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Non-volatile registers aware instruction selection for embedded systems.

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[DOI]

Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Wear-leveling for PCM main memory on embedded system via page management and process scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Energy efficient routing techniques with guaranteed reliability based on multi-level uncertain graph.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

On self-timed ring for consistent mapping and maximum throughput.

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[DOI]

Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Minimum-cost data allocation with guaranteed probability on multiple types of memory.

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[DOI]

Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Joint Convergecast and Power Allocation in Wireless Sensor Networks.

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[DOI]

Proceedings of the 15th International Conference on Parallel and Distributed Computing, 2014

2013

Optimizing Data Placement of Loops for Energy Minimization with Multiple Types of Memories.

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[DOI]

J. Signal Process. Syst., 2013

Efficient Loop Scheduling for Chip Multiprocessors with Non-Volatile Main Memory.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2013

Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Write activity reduction on non-volatile main memories for embedded chip multiprocessors.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

Data Placement and Duplication for Embedded Multicore Systems With Scratch Pad Memory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory.

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[DOI]

J. Syst. Archit., 2013

Accurate age counter for wear leveling on non-volatile based main memory.

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[DOI]

Des. Autom. Embed. Syst., 2013

A content-aware writing mechanism for reducing energy on non-volatile memory based embedded storage systems.

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[DOI]

Des. Autom. Embed. Syst., 2013

Effective file data-block placement for different types of page cache on hybrid main memory architectures.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2013

Optimal data allocation algorithm for loop-centric applications on scratch-PAD memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Optimizing task assignment for heterogeneous multiprocessor system with guaranteed reliability and timing constraint.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

A space-based wear leveling for PCM-based embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

Efficient task assignment and scheduling for MPSoC DSPS with VS-SPM considering concurrent accesses through data allocation.

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[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2013

Software enabled wear-leveling for hybrid PCM main memory on embedded systems.

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[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Curling-PCM: Application-specific wear leveling for phase change memory based embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Minimizing Access Cost for Multiple Types of Memory Units in Embedded Systems Through Data Allocation and Scheduling.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2012

Memory access schedule minimization for embedded systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 2012

General Loop Fusion Technique with Improved Timing Performance and Minimal Code Size.

[BibT_eX]

Int. J. Comput. Their Appl., 2012

Optimizing Data Allocation for Loops on Embedded Systems with Scratch-Pad Memory.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012

Optimal Assignment for Tree-Structure Task Graph on Heterogeneous Multicore Systems Considering Time Constraint.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

Optimizing Data Allocation and Memory Configuration for Non-Volatile Memory Based Hybrid SPM on Embedded CMPs.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Loop scheduling optimization for chip-multiprocessors with non-volatile main memory.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

Efficient Task Assignment on Heterogeneous Multicore Systems Considering Communication Overhead.

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[DOI]

Proceedings of the Algorithms and Architectures for Parallel Processing, 2012

PRR: A low-overhead cache replacement algorithm for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Loop Distribution and Fusion with Timing and Code Size Optimization.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2011

Write Activity Minimization for Nonvolatile Main Memory Via Scheduling and Recomputation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Variable assignment and instruction scheduling for processor with multi-module memory.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2011

Optimal Data Placement for Memory Architectures with Scratch-Pad Memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on Trust, 2011

Optimal Data Allocation for Scratch-Pad Memory on Embedded Multi-core Systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Parallel Processing, 2011

Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory.

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[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Variable Length Pattern Matching for Hardware Network Intrusion Detection System.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2010

Algorithms for Optimally Arranging Multicore Memory Structures.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2010

Optimal scheduling to minimize non-volatile memory access time with hardware cache.

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[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Minimizing write activities to non-volatile memory via scheduling and recomputation.

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[DOI]

Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

2008

Timing optimization via nest-loop pipelining considering code size.

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[DOI]

Microprocess. Microsystems, 2008

2007

Analysis and algorithms design for the partition of large-scale adaptive mobile wireless networks.

[BibT_eX]

[DOI]

Comput. Commun., 2007

Parallel Network Intrusion Detection on Reconfigurable Platforms.

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[DOI]

Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2007

2006

Loop scheduling with timing and switching-activity minimization for VLIW DSP.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

Optimizing Address Assignment and Scheduling for DSPs With Multiple Functional Units.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Security Protection and Checking for Embedded System Integration against Buffer Overflow Attacks via Hardware/Software.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Design optimization and space minimization considering timing and code size via retiming and unfolding.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2006

Algorithms and analysis of scheduling for loops with minimum switching.

[BibT_eX]

[DOI]

Int. J. Comput. Sci. Eng., 2006

Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network.

[BibT_eX]

[DOI]

Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability.

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[DOI]

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005

Efficient Assignment and Scheduling for Heterogeneous DSP Systems.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2005

Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems.

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Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2005

Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Parallel Architectures, 2005

Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005

Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs.

[BibT_eX]

[DOI]

Proceedings of the Embedded and Ubiquitous Computing, 2005

High-level synthesis for DSP applications using heterogeneous functional units.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Efficient variable partitioning and scheduling for DSP processors with multiple memory modules.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2004

Efficient Algorithms for Dynamic Update of Shortest Path Tree in Networking.

[BibT_eX]

Int. J. Comput. Their Appl., 2004

Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors.

[BibT_eX]

[DOI]

Int. J. High Perform. Comput. Netw., 2004

Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

Dynamic Update of Shortest Path Tree in OSPF.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Parallel Architectures, 2004

Approximation Algorithms Design for Disk Partial Covering Problem.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Parallel Architectures, 2004

Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units.

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[DOI]

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Timing Optimization of Nested Loops Considering Code Size for DSP Applications.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on Parallel Processing (ICPP 2004), 2004

Dynamic shortest path tree update for multiple link state decrements.

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[DOI]

Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures.

[BibT_eX]

[DOI]

Proceedings of the Embedded and Ubiquitous Computing, 2004

General loop fusion technique for nested loops considering timing and code size.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Compilers, 2004

Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

Loop Fusion via Retiming for DSP Applications.

[BibT_eX]

Proceedings of the ISCA 17th International Conference on Parallel and Distributed Computing Systems, 2004

2003

Code size reduction technique and implementation for software-pipelined DSP applications.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2003

An Integrated Framework of Design Optimization and Space Minimization for DSP applications.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Loop scheduling for minimizing schedule length and switching activities.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Design space minimization with timing and code size optimization for embedded DSP.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Defending Embedded Systems Against Buffer Overflow via Hardware/Software.

[BibT_eX]

[DOI]

Proceedings of the 19th Annual Computer Security Applications Conference (ACSAC 2003), 2003

Design and Analysis of Improved Shortest Path Tree Update for Network Routing.

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Proceedings of the ISCA 16th International Conference on Parallel and Distributed Computing Systems, 2003

2002

Analysis and Algorithms for Partitioning of Large-scale Adaptive Mobile Networks.

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Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Performance optimization of multiple memory architectures for DSP.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP.

[BibT_eX]

[DOI]

Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002

2001

Scheduling and partitioning for multiple loop nests.

[BibT_eX]

[DOI]

Zhong Wang

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Minimum dynamic update for shortest path tree construction.

[BibT_eX]

[DOI]

Proceedings of the Global Telecommunications Conference, 2001

Efficient Update of Shortest Path Algorithms for Network Routing.

[BibT_eX]