Qilin Zheng
Orcid: 0000-0002-5593-1369
According to our database1,
Qilin Zheng
authored at least 25 papers
between 2018 and 2024.
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Bibliography
2024
A Survey: Collaborative Hardware and Software Design in the Era of Large Language Models.
CoRR, 2024
SiDA: Sparsity-Inspired Data-Aware Serving for Efficient and Scalable Large Mixture-of-Experts Models.
Proceedings of the Seventh Annual Conference on Machine Learning and Systems, 2024
Hybrid Digital/Analog Memristor-based Computing Architecture for Sparse Deep Learning Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
NDSEARCH: Accelerating Graph-Traversal-Based Approximate Nearest Neighbor Search through Near Data Processing.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
Improving the Efficiency of In-Memory-Computing Macro with a Hybrid Analog-Digital Computing Mode for Lossless Neural Network Inference.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
EMS-i: An Efficient Memory System Design with Specialized Caching Mechanism for Recommendation Inference.
ACM Trans. Embed. Comput. Syst., October, 2023
SpikeSen: Low-Latency In-Sensor-Intelligence Design With Neuromorphic Spiking Neurons.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
IEEE J. Solid State Circuits, 2023
In-Storage Acceleration of Graph-Traversal-Based Approximate Nearest Neighbor Search.
CoRR, 2023
Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-based DNN Accelerators.
CoRR, 2023
Accelerating Sparse Attention with a Reconfigurable Non-volatile Processing-In-Memory Architecture.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Improving the Robustness and Efficiency of PIM-Based Architecture by SW/HW Co-Design.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Sci. China Inf. Sci., 2022
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2020
MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory Block.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Enhance the Robustness to Time Dependent Variability of ReRAM-Based Neuromorphic Computing Systems with Regularization and 2R Synapse.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning.
Proceedings of the Non-Volatile Memory Technology Symposium, 2018