Qifeng Huang
Orcid: 0000-0003-1830-0143
According to our database1,
Qifeng Huang
authored at least 11 papers
between 2003 and 2024.
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Bibliography
2024
The Error Analysis of Bit Weight Self-Calibration Methods for High-Resolution SAR ADCs.
IEEE Trans. Very Large Scale Integr. Syst., November, 2024
An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation.
IEEE Trans. Very Large Scale Integr. Syst., October, 2024
An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024
An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved SAR ADC With a Centralized Sampling Frontend.
IEEE Trans. Very Large Scale Integr. Syst., July, 2024
A 16b 5MS/s 93.7dB-SNDR SAR ADC with a Split Sampling Technique and SRM-Assisted Self-Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2017
Proceedings of the International Conference on Security, Pattern Analysis, and Cybernetics, 2017
2015
Path scheduling for multi-AGV system based on two-staged traffic scheduling scheme and genetic algorithm.
J. Comput. Methods Sci. Eng., 2015
Proceedings of the IEEE International Conference on Advanced Intelligent Mechatronics, 2015
2005
Proceedings of the 5th International Symposium on Cluster Computing and the Grid (CCGrid 2005), 2005
2003
J. Comput. Sci. Technol., 2003