Qiaosha Zou

Orcid: 0000-0001-6662-4316

According to our database1, Qiaosha Zou authored at least 24 papers between 2011 and 2024.

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Bibliography

2024
BAP: Bilateral asymptotic pruning for optimizing CNNs on image tasks.
Inf. Sci., 2024

Frequency Adaptive Normalization For Non-stationary Time Series Forecasting.
CoRR, 2024

2023
Accelerating Distributed GNN Training by Codes.
IEEE Trans. Parallel Distributed Syst., September, 2023

AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

Augmenting aspect-level sentiment classification with distance-related local context input.
J. Supercomput., July, 2023

2022
SAIL: A Deep-Learning-Based System for Automatic Gait Assessment From TUG Videos.
IEEE Trans. Hum. Mach. Syst., 2022

The Spike Gating Flow: A Hierarchical Structure Based Spiking Neural Network for Online Gesture Recognition.
CoRR, 2022

2021
Single-Pass On-Line Event Detection in Twitter Streams.
Proceedings of the ICMLC 2021: 13th International Conference on Machine Learning and Computing, 2021

Systolic-Array Deep-Learning Acceleration Exploring Pattern-Indexed Coordinate-Assisted Sparsity for Real-Time On-Device Speech Processing.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

2017
Thermomechanical Stress-Aware Management for 3-D IC Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Overview of 3-D Architecture Design Opportunities and Techniques.
IEEE Des. Test, 2017

2016
Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Heterogeneous architecture design with emerging 3D and non-volatile memory technologies.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Compact models and model standard for 2.5D and 3D integration.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

TSV power supply array electromigration lifetime analysis in 3D ICS.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Designing vertical bandwidth reconfigurable 3D NoCs for many core systems.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Cost-driven 3D design optimization with metal layer reduction technique.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Low power multi-level-cell resistive memory design with incomplete data mapping.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Thermomechanical stress-aware management for 3D IC designs.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
System-level design space exploration for three-dimensional (3D) SoCs.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011


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