Qianxian Liao

According to our database, Qianxian Liao authored at least 2 papers between 2023 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

14.7 A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS.

Liqun Feng, Xuansheng Ji, Longhao Kuang, Qianxian Liao, Su Han, Jiahao Zhao, Woogeun Rhee, Zhihua Wang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

A Low-Voltage Bias-Current-Free Pseudo-Differential Hybrid PLL Using a Time-Interleaving Flip-Flop Phase Detector.

Liqun Feng, Qianxian Liao, Woogeun Rhee, Zhihua Wang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023