Qianneng Zhou

According to our database1, Qianneng Zhou authored at least 10 papers between 2006 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2022
VLSI design of multiclass classification using sparse extreme learning machine for epilepsy and seizure detection.
IEICE Electron. Express, 2022

2021
Hardware Design of Gaussian Kernel Function for Non-Linear SVM Classification.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2017
High-order curvature-compensated CMOS bandgap voltage reference.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A PPG Signal De-Noising Method Based on the DTCWT and the Morphological Filtering.
Proceedings of the 12th International Conference on Signal-Image Technology & Internet-Based Systems, 2016

2014
Designing Optimized Imprecise Fixed-Point Arithmetic Circuits Specified by polynomials with Various Constraints.
J. Circuits Syst. Comput., 2014

A Sub-1V High-PSRR Piecewise-Linear Bandgap Reference.
J. Comput., 2014

Design of Modulation and Packet Detection in Body Area Networks.
J. Comput., 2014

2007
On-Chip Voltage Down Converter Based on Moderate Inversion for Low- Power VLSI Chips.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
On-chip 3.3V-to-1.8V voltage down converter for low-power VLSI chips.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Embedded DC-DC Voltage Down Converter for Low-Power VLSI Chip.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006


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