Qiang Zhao
Orcid: 0000-0002-0278-5804Affiliations:
- Anhui University, School of Integrated Circuits, Hefei, China
According to our database1,
Qiang Zhao
authored at least 27 papers
between 2018 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A Computing In-Memory Multibit Multiplication Based on Decoupling and In-Array Storing.
IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024
IEEE Trans. Very Large Scale Integr. Syst., May, 2024
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies.
IEEE Trans. Very Large Scale Integr. Syst., April, 2024
Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
Microelectron. J., 2024
Microelectron. J., 2024
Microelectron. J., 2024
2023
Novel radiation-hardened-by-design (RHBD) 14T memory cell for aerospace applications in 65 nm CMOS technology.
Microelectron. J., November, 2023
A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023
IEEE J. Solid State Circuits, May, 2023
High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023
Microelectron. J., February, 2023
Four-branch Siamese network based on sketch-specific data augmentation for sketch recognition.
IET Image Process., February, 2023
Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments.
Int. J. Circuit Theory Appl., January, 2023
IEICE Electron. Express, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset.
Microelectron. J., 2022
IEICE Electron. Express, 2022
2021
Half-Select Disturb-Free 10T Tunnel FET SRAM Cell With Improved Noise Margin and Low Power Consumption.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing.
IEEE J. Solid State Circuits, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
2019
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS.
IEICE Electron. Express, 2019
An inverter chain with parallel output nodes for eliminating single-event transient pulse.
IEICE Electron. Express, 2019
IEICE Electron. Express, 2019
2018
A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination.
IEICE Electron. Express, 2018