Qiang Zhao

According to our database, Qiang Zhao authored at least 30 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

High-Performance Latch Designs of Double-Node-Upset Self-Recovery and Triple-Node-Upset Tolerance for Aerospace Applications.

Chunyu Peng, Lang Tian, Licai Hao, Qiang Zhao, Chenghu Dai, Zhiting Lin, Xiulong Wu

IEEE Trans. Aerosp. Electron. Syst., October, 2024

A Computing In-Memory Multibit Multiplication Based on Decoupling and In-Array Storing.

Jin Zhang, Zhongzhen Tong, Hao Wang, Xin Wang, Qiang Zhao, Jian Zhou, Jiaqun Wang, Zhiting Lin, Xiulong Wu

IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024

Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design.

Licai Hao, Yaling Wang, Yunlong Liu, Shiyu Zhao, Xinyi Zhang, Yang Li, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Yongliang Zhou, Chenghu Dai, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., May, 2024

Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies.

Licai Hao, Xinyi Zhang, Chenghu Dai, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Yongliang Zhou, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., April, 2024

Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory.

Li Liu, Dele Tai, Bin Qiang, Lijun Guan, Chunyu Peng, Chenghu Dai, Licai Hao, Wenjuan Lu, Zhiting Lin, Qiang Zhao, Xiulong Wu

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Design of polarity hardening SRAM for mitigating single event multiple node upsets.

Shiyu Zhao, Qiang Zhao, Licai Hao, Chunyu Peng, Yaling Wang, Wenjuan Lu, Zhiting Lin, Xiulong Wu

Microelectron. J., 2024

An 11-bit two-step column-shared ADC based on Flash/SS architecture for CMOS image sensor.

Qiang Zhao, Jitao Xu, Chunhui Fan, Ziming Wang, Ruitong Hu, Xin Li, Zhigang Li, Licai Hao, Chunyu Peng, Zhiting Lin, Xiulong Wu

Microelectron. J., 2024

Configurable in-memory computing architecture based on dual-port SRAM.

Yue Zhao, Yunlong Liu, Jian Zheng, Zhongzhen Tong, Xin Wang, Runru Yu, Xiulong Wu, Yongliang Zhou, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Zhiting Lin

Microelectron. J., 2024

Cross-coupled 4T2R multi-logic in-memory computing circuit design.

Zhiting Lin, Changxin Yue, Ke Li, Qiushi Feng, Siyan Li, Yue Zhao, Yuanyang Wang, Jiaqi Chen, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Chenghu Dai, Licai Hao, Xiulong Wu

Microelectron. J., 2024

A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC.

Zhiting Lin, Runru Yu, Da Huo, Qingchuan Zhu, Miao Long, Yongqi Qin, Yanchun Liu, Lintao Chen, Simin Wang, Ting Wang, Yousheng Xing, Zeshi Wen, Yu Liu, Xin Li, Chenghu Dai, Qiang Zhao, Chunyu Peng, Xiulong Wu

Microelectron. J., 2024

2023

Novel radiation-hardened-by-design (RHBD) 14T memory cell for aerospace applications in 65 nm CMOS technology.

Pengfei Li, Xiuying Wang, Yin Zhang, Haoyu Wang, Jianjie Lu, Qiang Zhao, Licai Hao, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Xiulong Wu

Microelectron. J., November, 2023

A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store.

Zhiting Lin, Shaoying Zhang, Qian Jin, Jianping Xia, Yunwei Liu, Kefeng Yu, Jian Zheng, Xiaoming Xu, Xing Fan, Ke Li, Zhongzhen Tong, Xiulong Wu, Wenjuan Lu, Chunyu Peng, Qiang Zhao

IEEE Trans. Very Large Scale Integr. Syst., June, 2023

In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations.

Zhiting Lin, Zhongzhen Tong, Fangming Wang, Jin Zhang, Yue Zhao, Peng Sun, Tian Xu, Cheng Zhang, Xingwei Li, Xiulong Wu, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Junning Chen

IEEE J. Solid State Circuits, May, 2023

High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications.

Zhiting Lin, Min Chen, Peng Sun, Xiulong Wu, Qiang Zhao, Wenjuan Lu, Chunyu Peng

IEEE Trans. Very Large Scale Integr. Syst., April, 2023

Design of radiation-hardened memory cell by polar design for space applications.

Licai Hao, Li Liu, Qi Shi, Bin Qiang, Zhengya Li, Nianlong Liu, Chenghu Dai, Qiang Zhao, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Xiulong Wu

Microelectron. J., February, 2023

Four-branch Siamese network based on sketch-specific data augmentation for sketch recognition.

Xiuying Wang, Qiang Zhao, Shoubiao Tan

IET Image Process., February, 2023

Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments.

Qiang Zhao, Hanwen Dong, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Junning Chen, Xiulong Wu

Int. J. Circuit Theory Appl., January, 2023

Radiation-hardened 14T SRAM cell by polar design for space applications.

Licai Hao, Bin Qiang, Chenghu Dai, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Li Liu, Qiang Zhao, Xiulong Wu, Fei Sun

IEICE Electron. Express, 2023

2022

Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing.

Yue Zhao, Zhiting Lin, Xiulong Wu, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Zhongzhen Tong, Junning Chen

IEEE Trans. Very Large Scale Integr. Syst., 2022

In-Memory Multibit Multiplication Based on Bitline Shifting.

Jin Zhang, Zhiting Lin, Xiulong Wu, Zhongzhen Tong, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Hongbiao Wu, Junning Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2022

An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset.

Yue Zhao, Jinkai Wang, Zhongzhen Tong, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Qiang Zhao, Zhiting Lin

Microelectron. J., 2022

Novel radiation-hardened latch design for space-radiation environments.

Qiang Zhao, Hanwen Dong, Licai Hao, Xiuying Wang, Chunyu Peng, Xiulong Wu

IEICE Electron. Express, 2022

2021

Half-Select Disturb-Free 10T Tunnel FET SRAM Cell With Improved Noise Margin and Low Power Consumption.

Zhiting Lin, Luanyun Li, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Qiang Zhao

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing.

Zhiting Lin, Honglan Zhan, Zhongwei Chen, Chunyu Peng, Xiulong Wu, Wenjuan Lu, Qiang Zhao, Xuan Li, Junning Chen

IEEE J. Solid State Circuits, 2021

2020

Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications.

Qiang Zhao, Chunyu Peng, Junning Chen, Zhiting Lin, Xiulong Wu

IEEE Trans. Very Large Scale Integr. Syst., 2020

2019

Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application.

Chunyu Peng, Jiati Huang, Changyong Liu, Qiang Zhao, Songsong Xiao, Xiulong Wu, Zhiting Lin, Junning Chen, Xuan Zeng

IEEE Trans. Very Large Scale Integr. Syst., 2019

Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS.

Qiang Zhao, Chunyu Peng, Changyong Liu, Xiulong Wu

IEICE Electron. Express, 2019

An inverter chain with parallel output nodes for eliminating single-event transient pulse.

Changyong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu

IEICE Electron. Express, 2019

A single event upset tolerant latch with parallel nodes.

Changyong Liu, Nianlong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu

IEICE Electron. Express, 2019

2018

A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination.

Changyong Liu, Chunyu Peng, Zhiting Lin, Xiulong Wu, Ziyang Chen, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu

IEICE Electron. Express, 2018