Qiang Li

IEEE Trans. Circuits Syst. II Express Briefs, November, 2024

Deep Learning Assisted Multiuser MIMO Load Modulated Systems for Enhanced Downlink mmWave Communications.

[BibT_eX]

[DOI]

IEEE Trans. Wirel. Commun., July, 2024

A 0.8-V Supply, 1.58% 3σ-Accuracy, 1.9-μW Bandgap Reference in 0.13-μm CMOS.

[BibT_eX]

[DOI]

Yirui Cao

Haoyu Zhuang

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

A 20 MHz, 98.7 dB-SFDR, Capacitively Degenerated Dynamic Amplifier Without Bias Voltage Calibrations.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

A low power 16-bit 50 MS/s pipeline ADC with 104 dB SFDR in 0.18 μm CMOS.

[BibT_eX]

[DOI]

Microelectron. J., 2024

2023

A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., August, 2023

TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, March, 2023

On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2023

Improved Dynamic Comparator With Adaptive Delay Line for the Latch Conduction and Regenerative Feedback Assisted FIA.

[BibT_eX]

[DOI]

Feng Tai

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Bitwise ELD Compensation under Integrator Nonidealities in ΔΣ Modulators.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

A Low-Noise and Settling-Enhanced Switched-Capacitor Amplifier With Correlated Level Shifting and Bandwidth Switching.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 128-GS/s Timing-Robust Sampling Architecture Exploiting Analog FFT.

[BibT_eX]

[DOI]

Xingchen Chao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 0.69-Noise-Efficiency-Factor 4 x-Current-Reuse Dynamic Comparator with A Stacking FIA.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022

Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 130-dB CMRR Instrumentation Amplifier With Common-Mode Replication.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

An On-Chip Power-Supply Noise Analyzer With Compressed Sensing and Enhanced Quantization.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

16- and 64-Point Analog Computing of FFT with Improved Performance and Efficiency.

[BibT_eX]

[DOI]

Jingjing Li

Xingchen Chao

Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

A 13-bit 1-MS/s SAR ADC With Rotation-Based Mismatch Error Cancellation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Maximizing the Inter-Stage Gain in CT 0-X MASH Delta-Sigma-Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 100dB-TCMRR 8-Channel Bio-Potential Front-End with Multi-Channel Common-Mode Replication.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Bitwise ELD Compensation in Δ∑ Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 4.2-to-5.6 GHz Transformer-Based PMOS-only Stacked-gm VCO in 28-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021

A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

ECDR$^{2}$2: Error Corrector and Detector Relocation Router for Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2021

An AC-Coupled Instrumentation Amplifier Achieving 110-dB CMRR at 50 Hz With Chopped Pseudoresistors and Successive-Approximation-Based Capacitor Trimming.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2021

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2021

15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Sampling Speed Enhancement Technique for Near-Threshold SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Ku-Band SiGe Phased-Array Transceiver with 6-Bit Phase and Attenuation Control.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Low-Power RC Oscillator with Offset and Path Delay Cancellation.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

Teaching Logic and Sequential Cell Characterization in Digital Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the ICETT 2021: 7th International Conference on Education and Training Technologies, Macau, China, April 14, 2021

A Comparator Speed Enhancement Technique for Near- and Sub-Threshold ADCs.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Electronics, 2021

A 9.08 ENOB 10b 400MS/s Subranging SAR ADC with Subsetted CDAC and PDAS in 40nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 47th ESSCIRC 2021, 2021

A 640×512 30μm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-out Integrated Circuit with Fully On-chip Image Algorithm Pixel-Level Calibration.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2020

A Fully Integrated LDO With 50-mV Dropout for Power Efficiency Optimization.

[BibT_eX]

[DOI]

Xiaofei Ma

Yan Lu

IEEE Trans. Circuits Syst. II Express Briefs, 2020

An NMOS Digital LDO With NAND-Based Analog-Assisted Loop in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

A Probabilistic Prediction-Based Fixed-Width Booth Multiplier for Approximate Computing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

A 14-bit 4-MS/s VCO-Based SAR ADC With Deep Metastability Facilitated Mismatch Calibration.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

23.7 A 130dB CMRR Instrumentation Amplifier with Common-Mode Replication.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

25.4 A Scalable 20GHz On-Die Power-Supply Noise Analyzer with Compressed Sensing.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Efficient Design-for-Test Approach for Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Inverter-Based Subthreshold Amplifier Techniques and Their Application in 0.3-V $\Delta\Sigma$ -Modulators.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

A 0.5-1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Online Path-Based Test Method for Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Loss-Compensated 5-Bit Ka-Band Digital Phase Shifter with Low RMS Phase/Gain Error Over Wide Temperature Ranges.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 12-bit 30MS/s SAR ADC with VCO-Based Comparator and Split-and-Recombination Redundancy for Bypass Logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Multi-Slice VCO-based Quantizer for On-Chip Power Supply Noise Analysis Achieving 0.11 (mV)2/sqrt(MHz) Noise Floor.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018

A 0.4-V Gm-C Proportional-Integrator-Based Continuous-Time ΔΣ Modulator With 50-kHz BW and 74.4-dB SNDR.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

A 0.5-1.1V 10B Adaptive Bypassing SAR ADC Utilizing Oscillation Cycle Information of VCO-Based Comparator.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A >3GHz ERBW 1.1GS/S 8B Two-Sten SAR ADC with Recursive-Weight DAC.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Optimal Slope Ranking: An Approximate Computing Approach for Circuit Pruning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Micro-Architecture Design for Low Overhead Fault Tolerant Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Energy-Efficient Approximate DCT for Wireless Capsule Endoscopy Application.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Delta-Measurement Low-Power SAR ADC Architecture with Adaptive Threshold-First Switching.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Optimizing dynamic mapping techniques for on-line NoC test.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

A lifetime-aware mapping algorithm to extend MTTF of Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

A Voltage Swing Robust Pseudo-Resistor Structure for Biomedical Front-end Amplifier.

[BibT_eX]

[DOI]

Sanfeng Zhang

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

Minimizing the system impact of router faults by means of reconfiguration and adaptive routing.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A low latency fault tolerant transmission mechanism for Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Optimization of the amplifier's input-referred noise for high resolution comparators.

[BibT_eX]

[DOI]

Qichao He

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Phase-error cancellation technique for fast-lock phase-locked loop.

[BibT_eX]

[DOI]

Haiqi Liu

IET Circuits Devices Syst., 2016

A wearable ear-EEG recording system based on dry-contact active electrodes.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping.

[BibT_eX]

[DOI]

Proceedings of the Fourth ACM International Workshop on Many-core Embedded Systems, 2016

Optimizing the location of ECC protection in network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Fast-settling technique under large electrode offset in integrated biopotential amplifiers.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015

A High-Speed Energy-Efficient Segmented Prequantize and Bypass DAC for SAR ADCs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Design Considerations of Ultralow-Voltage Self-Calibrated SAR ADC.

[BibT_eX]

[DOI]

Hai Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Energy efficient comparator for successive approximation register ADCs with application to wireless sensor networks.

[BibT_eX]

[DOI]

Int. J. Sens. Networks, 2015

Central span switching structure for SAR ADC with improved linearity and reduced DAC power.

[BibT_eX]

[DOI]

Junfeng Gao

IEICE Electron. Express, 2015

300mV 50kHz 75.9dB SNDR CT ΔΣ Modulator with Inverter-based Feedforward OTAs.

[BibT_eX]

[DOI]

Lishan Lv

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A fast and energy efficient binary-to-pseudo CSD converter.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An 890 mW stacked power amplifier using SiGe HBTs for X-band multifunctional chips.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC Conference 2015, 2015

2014

A energy-efficient high speed segmented prequantize and bypass DAC for SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A low-power, CT sigma-delta modulator with a 2b/cycle SAR quantizer.

[BibT_eX]

[DOI]

Lishan Lv

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A digital calibration technique for multi-bit-per-stage pipelined ADC.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A 10-bit 150MS/s SAR ADC with parallel segmented DAC in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 250mV 77dB DR 10kHz BW SC ΔΣ Modulator Exploiting Subthreshold OTAs.

[BibT_eX]

[DOI]

Zhiliang Qiao

Proceedings of the ESSCIRC 2014, 2014

2013

Blind-LMS based digital background calibration for a 14-Bit 200-MS/s pipelined ADC.

[BibT_eX]

[DOI]

Yajuan He

Bo Chen

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Hardware-efficient parallel structures for linear-phase FIR digital filter.

[BibT_eX]

[DOI]

Jingjing Tian

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A 0.25V 97.8fJ/c.-s. 86.5dB SNDR SC ΔΣ modulator in 0.13µm CMOS.

[BibT_eX]

[DOI]

Zhiliang Qiao

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

High performance SAR ADC with offset and noise tolerance.

[BibT_eX]

[DOI]

Junfeng Gao

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A 13-bit 200MS/s PIPELINE ADC in 0.13µm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A 0.5V rate-resolution scalable SAR ADC with 63.7dB SFDR.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

An Ultrafast Adaptively Biased Capacitorless LDO With Dynamic Charging Control.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

A fast-convergence and robust digital calibration algorithm for a 14-bit 200-MS/s hybrid pipelined-SAR ADC.

[BibT_eX]

[DOI]

Shan Qing

Guang-Jun Li

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A fast correlation based background digital calibration for pipelined ADCs.

[BibT_eX]

[DOI]

Chuan-Ping Yan

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

A multi-rate SerDes transceiver for IEEE 1394b applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Waveform distortion performance evaluation using practical antennas in deterministic multipath impulse radio channels.

[BibT_eX]

[DOI]

IET Commun., 2011

2008

Antenna-in-Package and Transmit-Receive Switch for Single-Chip Radio Transceivers of Differential Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

2007

CMOS T/R Switch Design: Towards Ultra-Wideband and Higher Frequency.

[BibT_eX]

[DOI]