Qi Yu

Orcid: 0000-0002-0490-0749

Affiliations:

University of Electronic Science and Technology of China, State Key Laboratory of Electronic Thin Films and Integrated Devices, Chengdu, China (PhD 2010)

According to our database¹, Qi Yu authored at least 64 papers between 2013 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

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Bibliography

2024

Spatio-Temporal Fusion Spiking Neural Network for Frame-Based and Event-Based Camera Sensor Fusion.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput. Intell., June, 2024

Floating-Point Approximation Enabling Cost-Effective and High-Precision Digital Implementation of FitzHugh-Nagumo Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., April, 2024

Fullerene-Inspired Efficient Neuromorphic Network-on-Chip Scheme.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

An Adaptive Common-Mode Cancellation Biopotential Amplifier for Two-Electrode Dynamic ECG Recording.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

Achieving High Core Neuron Density in a Neuromorphic Chip Through Trade-off Among Area, Power Consumption, and Data Access Bandwidth.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., December, 2023

A 0.053 mm<sup>2</sup> 10-bit 10-ks/s 40-nW SAR ADC with pseudo single ended switching procedure for bio-related applications.

[BibT_eX]

[DOI]

Microelectron. J., September, 2023

A 3-5 GHz, 108fs-RMS jitter, clock receiver circuit for time-interleaved ADCs with a sampling rate of 4 GS/s.

[BibT_eX]

[DOI]

Microelectron. J., September, 2023

Batch normalization-free weight-binarized SNN based on hardware-saving IF neuron.

[BibT_eX]

[DOI]

Neurocomputing, August, 2023

Ultra-High-Speed Accelerator Architecture for Convolutional Neural Network Based on Processing-in-Memory Using Resistive Random Access Memory.

[BibT_eX]

[DOI]

Sensors, March, 2023

An Area- and Energy-Efficient Spiking Neural Network With Spike-Time-Dependent Plasticity Realized With SRAM Processing-in-Memory Macro and On-Chip Unsupervised Learning.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., February, 2023

A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

A programmable analog front-end with independent biasing technique for ECG signal acquisition.

[BibT_eX]

[DOI]

Microelectron. J., 2023

A 59.99dB SNDR 1.13mW Ping-pong NS SAR ADC for 3-D Transesophageal Echocardiography.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

Ultra-low-power and High-accuracy CMOS Temperature Sensor.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Programmable High-Voltage Pulse Transmitter Circuit for 3-D Miniature Ultrasound Probes.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

A Co-Designed Neuromorphic Chip With Compact (17.9K F<sup>2</sup>) and Weak Neuron Number-Dependent Neuron/Synapse Modules.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., December, 2022

A Code-Recombination Algorithm-Based ADC With Feature Extraction for WBSN Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

A 12bit 250 MS/s 5.43fJ/conversion-step SAR ADC with adaptive asynchronous logic in 28 nm CMOS.

[BibT_eX]

[DOI]

Microelectron. J., 2022

A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

2021

A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

A +0.44°C/-0.4°C Inaccuracy Temperature Sensor With Multi-Threshold MOSFET-Based Sensing Element and CMOS Thyristor-Based VCO.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Quantized STDP-based online-learning spiking neural network.

[BibT_eX]

[DOI]

Neural Comput. Appl., 2021

Direct training of hardware-friendly weight binarized spiking neural network with surrogate gradient learning towards spatio-temporal event-based dynamic data recognition.

[BibT_eX]

[DOI]

Neurocomputing, 2021

Design of a constant loop bandwidth phase-locked loop based on artificial neural network.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2021

A13b-ENOB Third-Order Noise-Shaping SAR ADC using a Hybrid Error-Control Structure.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

A Second-Order Passive Noise-Shaping SAR ADC Using the LMS-Based Mismatch Calibration.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

A 12-Bit Dynamic Tracking Algorithm-Based SAR ADC With Real-Time QRS Detection.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A High Area-Efficiency 14-bit SAR ADC With Hybrid Capacitor DAC for Array Sensors.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Application of Deep Compression Technique in Spiking Neural Network Chip.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2020

A second-order noise-shaping SAR ADC with error-feedback structure and data weighted averaging.

[BibT_eX]

[DOI]

Microelectron. J., 2020

An energy-efficient deep convolutional neural networks coprocessor for multi-object detection.

[BibT_eX]

[DOI]

Microelectron. J., 2020

Switching sequence optimization for gradient errors compensation in the current-steering DAC design.

[BibT_eX]

[DOI]

Microelectron. J., 2020

A nano-watt power-on reset circuit with Brown-Out detection capability.

[BibT_eX]

[DOI]

Microelectron. J., 2020

STBNN: Hardware-friendly spatio-temporal binary neural network with high pattern recognition accuracy.

[BibT_eX]

[DOI]

Neurocomputing, 2020

A Kalman filtering based adaptive threshold algorithm for QRS complex detection.

[BibT_eX]

[DOI]

Biomed. Signal Process. Control., 2020

A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors.

[BibT_eX]

[DOI]

IEEE Access, 2020

Design of AM Self-Capacitive Transparent Touch Panel Based on a-IGZO Thin-Film Transistors.

[BibT_eX]

[DOI]

IEEE Access, 2020

A 10-Bit Fully-Predictive ADC with Code-Recombination Algorithm in Transducing Sensor Node Signals.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Predictive SAR ADC with two-step loading technology for energy reduction.

[BibT_eX]

[DOI]

Microelectron. J., 2019

A Full-Band Timing Mismatch Calibration Technique in Time-Interleaved ADCs.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2019

A Neuromorphic-Hardware Oriented Bio-Plausible Online-Learning Spiking Neural Network Model.

[BibT_eX]

[DOI]

IEEE Access, 2019

Implementation of a Low Noise Amplifier With Self-Recovery Capability.

[BibT_eX]

[DOI]

IEEE Access, 2019

Study of Recall Time of Associative Memory in a Memristive Hopfield Neural Network.

[BibT_eX]

[DOI]

IEEE Access, 2019

Design of a Neural Network-Based VCO With High Linearity and Wide Tuning Range.

[BibT_eX]

[DOI]

IEEE Access, 2019

A Low-Power and Area-Efficient 14-bit SAR ADC with Hybrid CDAC for Array Sensors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Low Voltage 10-Bit Non-Binary 2B/Cycle Time and Voltage Based SAR ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Calibration Technique for Two-Step Single-Slope Analog-to-Digital Converter.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

A Dynamic Tracking Algorithm Based SAR ADC in Bio-Related Applications.

[BibT_eX]

[DOI]

IEEE Access, 2018

Predicting House Price With a Memristor-Based Artificial Neural Network.

[BibT_eX]

[DOI]

IEEE Access, 2018

The Effects of Comparator Dynamic Capacitor Mismatch in SAR ADC and Correction.

[BibT_eX]

[DOI]

IEEE Access, 2018

Realization of a Power-Efficient Transmitter Based on Integrated Artificial Neural Network.

[BibT_eX]

[DOI]

IEEE Access, 2018

2015

A Supply Voltage and Temperature Variation-Tolerant Relaxation Oscillator for Biomedical Systems Based on Dynamic Threshold and Switched Resistors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Hybrid LED driver for multi-channel output with high consistency.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Multiscaling coefficients Technique for gain error Background Calibration in Pipelined ADC.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2014

A dithering Technique for Sha_less Pipelined ADC.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2014

Digital Background Calibration for Timing skew in Time-Interleaved ADC.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2014

A digital background calibration technique for SAR ADC based on capacitor swapping.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

A 10-bit 100MS/s subrange SAR ADC with time-domain quantization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Vco-Based continuous-Time Sigma Delta ADC Based on a Dual-VCO-quantizer-Loop Structure.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2013

A process variation insensitive bandgap reference with self-calibration technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Qi Yu

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