Qi Liu
Orcid: 0000-0001-7062-831XAffiliations:
- Fudan University, State Key Laboratory of ASIC and System, Frontier Institute of Chip and System, Shanghai, China
- Chinese Academy of Sciences, Institute of Microelectronics, Beijing, China
- Anhui University, College of Electronics and Technology, China (PhD 2010)
According to our database1,
Qi Liu
authored at least 63 papers
between 2006 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
SLAM-CIM: A Visual SLAM Backend Processor With Dynamic-Range-Driven-Skipping Linear-Solving FP-CIM Macros.
IEEE J. Solid State Circuits, November, 2024
FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024
ANP-I: A 28-nm 1.5-pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-0.1-μ J/Sample On-Chip Learning for Edge-AI Applications.
IEEE J. Solid State Circuits, August, 2024
A Scalable Area-Efficient Low-Delay Asynchronous AER Circuits Design for Neuromorphic Chips.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer.
IEEE Trans. Very Large Scale Integr. Syst., February, 2024
Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge.
IEEE Trans. Very Large Scale Integr. Syst., February, 2024
A 9-Mb HZO-Based Embedded FeRAM With 10-Cycle Endurance and 5/7-ns Read/Write Using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier.
IEEE J. Solid State Circuits, January, 2024
A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration.
Integr., 2024
Continuous-Time Digital Twin with Analogue Memristive Neural Ordinary Differential Equation Solver.
CoRR, 2024
CoRR, 2024
Resistive Memory-based Neural Differential Equation Solver for Score-based Diffusion Model.
CoRR, 2024
34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 128×128 CMOS SPAD Receiver for 500Mbps Free Space Optical Communication with Column-wise Decoding and Fast Spot Tracking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
High-efficient and Comprehensive Modeling of MFIM Ferroelectric Tunnel Junctions for Non-volatile/Volatile Applications.
Proceedings of the IEEE International Memory Workshop, 2024
CAMPER: Exploring the Potential of Content Addressable Memory for 3D Point Cloud Efficient Range Search.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
CEDAR: Computing-in-pixel Edge-aware Detection and Reconstruction Architecture for High-resolution 3D Imaging.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
A 32×32 Flash LiDAR SPAD Sensor with Up-to-1kfps Motional Target Detection by Threshold-adaptive 2D Dynamic Vision.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A 13b 500MS/s Dual-Residue Pipelined-SAR ADC with One-Way Switching Capacitive Interpolation and Background Offset Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
Multicore Spiking Neuromorphic Chip in 180-nm With ReRAM Synapses and Digital Neurons.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023
Ultralow-Power Compact Artificial Synapse Based on a Ferroelectric Fin Field-Effect Transistor for Spatiotemporal Information Processing.
Adv. Intell. Syst., November, 2023
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference.
IEEE J. Solid State Circuits, October, 2023
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier.
IEEE J. Solid State Circuits, October, 2023
An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023
Nat. Mac. Intell., February, 2023
Random resistive memory-based deep extreme point learning machine for unified visual processing.
CoRR, 2023
Resistive memory-based zero-shot liquid state machine for multimodal event data learning.
CoRR, 2023
ANP-I: A 28nm 1.5pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-O.1 μJ/Sample On-Chip Learning for Edge-AI Applications.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 9Mb HZO-Based Embedded FeRAM with 10<sup>12</sup>-Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
TiPU: A Spatial-Locality-Aware Near-Memory Tile Processing Unit for 3D Point Cloud Neural Network.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Adv. Intell. Syst., December, 2022
IEEE Trans. Cybern., 2022
High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
A neuromorphic core based on threshold switching memristor with asynchronous address event representation circuits.
Sci. China Inf. Sci., 2022
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 11.6μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A 200M-Query-Vector/s Computing-in-RRAM ADC-less k-Nearest-Neighbor Accelerator with Time-Domain Winner-Takes-All Circuits.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Sci. China Inf. Sci., 2021
Energy-Efficient Memristive Euclidean Distance Engine for Brain-Inspired Competitive Learning.
Adv. Intell. Syst., 2021
Sparsity-Aware Clamping Readout Scheme for High Parallelism and Low Power Nonvolatile Computing-in-Memory Based on Resistive Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
RRAM-based Analog-Weight Spiking Neural Network Accelerator with in-situ Learning for IoT Applications.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
An ultra-fast and high-precision VCO frequency calibration technique for fractional-N frequency synthesizers.
IEICE Electron. Express, 2020
Conditional Uncorrelation and Efficient Non-approximate Subset Selection in Sparse Regression.
CoRR, 2020
Adv. Intell. Syst., 2020
33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10<sup>-6</sup> Native Bit Error Rate.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
An Asynchronous AER Circuits with Rotation Priority Tree Arbiter for Neuromorphic Hardware with Analog Neuron.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the Handbook of Memristor Networks., 2019
2018
Sci. China Inf. Sci., 2018
2017
A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2010
Formation and annihilation of Cu conductive filament in the nonpolar resistive switching Cu/ZrO2: Cu/Pt ReRAM.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006