Punithavathi Duraiswamy

According to our database, Punithavathi Duraiswamy authored at least 6 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

GA evolved CGP configuration data for digital circuit design on embryonic architecture.

Gayatri Malhotra, Punithavathi Duraiswamy

Int. J. Hybrid Intell. Syst., 2023

2022

GA Evolved Configuration Data for Embryonic Architecture with Built-in Self-test.

Gayatri Malhotra, Punithavathi Duraiswamy, J. K. Kishore

Proceedings of the Intelligent Systems Design and Applications - 22nd International Conference on Intelligent Systems Design and Applications (ISDA 2022) Held December 12-14, 2022, 2022

2021

Single Stage Low Noise Inductor-Less TIA for RF Over Fiber Communication.

Vijay Kumar, G. Sai Saravanan, Punithavathi Duraiswamy, Shankar Kumar Selvaraja

IEEE Access, 2021

2020

Phase-orthogonal FIR filters: An efficient VLSI architecture for communication applications.

Punithavathi Duraiswamy, Satishkumar, Raghu, Shankar Kumar Selvaraja

IEICE Electron. Express, 2020

2012

Synchronous delay based UWB pulse generator in FPGA.

Punithavathi Duraiswamy, Xiao Li, Johan Bauwelinck, Jan Vandewege, Peter Vaes, Stephanie Teughels

IEICE Electron. Express, 2012

2011

Efficient implementation of 90° phase shifter in FPGA.

Punithavathi Duraiswamy, Johan Bauwelinck, Jan Vandewege

EURASIP J. Adv. Signal Process., 2011