Puneet Ramesh Savanur

According to our database, Puneet Ramesh Savanur authored at least 3 papers between 2015 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

A Fault Model to Detect Design Errors in Combinational Circuits.

Puneet Ramesh Savanur, Spyros Tragoudas

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2018

Threshold Voltage Extraction Using Static NBTI Aging.

Puneet Ramesh Savanur, Spyros Tragoudas

Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

2015

A BIST approach for counterfeit circuit detection based on NBTI degradation.

Puneet Ramesh Savanur, Phaninder Alladi, Spyros Tragoudas

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015