Puneet Gupta

IEEE Trans. Computers, April, 2024

DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems.

[BibT_eX]

[DOI]

Newsha Ardalani

ACM Trans. Design Autom. Electr. Syst., March, 2024

A 278-514M Event/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Cryogenic Alternative: CMOS Versus Dynamic-Based Logic.

[BibT_eX]

[DOI]

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Novel Energy-Efficient and Latency-Improved PVT Tolerant Read Scheme for SRAM Design in Video Processing and Machine Learning Applications.

[BibT_eX]

[DOI]

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

2023

REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

DRDebug: Automated Design Rule Debugging.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

Cost-Driven Hardware-Software Co-Optimization of Machine Learning Pipelines.

[BibT_eX]

[DOI]

CoRR, 2023

Training Neural Networks for Execution on Approximate Hardware.

[BibT_eX]

[DOI]

Shurui Li

CoRR, 2023

ReFOCUS: Reusing Light for Efficient Fourier Optics-Based Photonic Neural Network Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Chiplets: How Small is too Small?

[BibT_eX]

[DOI]

Alexander Graening

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration.

[BibT_eX]

[DOI]

Wojciech Romaszkan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Bit-serial Weight Pools: Compression and Arbitrary Precision Execution of Neural Networks on Resource Constrained Processors.

[BibT_eX]

[DOI]

Shurui Li

Proceedings of the Fifth Conference on Machine Learning and Systems, 2022

COMET: On-die and In-controller Collaborative Memory ECC Technique for Safer and Stronger Correction of DRAM Errors.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022

LAC: Learned Approximate Computing.

[BibT_eX]

[DOI]

Vaibhav Gupta

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Adaptive MRAM Write and Read with MTJ Variation Monitor.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2021

Batch Processing and Data Streaming Fourier-based Convolutional Neural Network Accelerator.

[BibT_eX]

[DOI]

Zibo Hu

Shurui Li

Russell L. T. Schwartz

Maria Solyanik-Gorgone

Mario Miscuglio

Volker J. Sorger

CoRR, 2021

SWIS - Shared Weight bIt Sparsity for Efficient Neural Network Acceleration.

[BibT_eX]

[DOI]

CoRR, 2021

A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM.

[BibT_eX]

[DOI]

Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Designing a 2048-Chiplet, 14336-Core Waferscale Processor.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Design Space Exploration for Chiplet-Assembly-Based Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

SLATE: A Secure Lightweight Entity Authentication Hardware Primitive.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2020

3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning.

[BibT_eX]

[DOI]

Wojciech Romaszkan

ACM Trans. Embed. Comput. Syst., 2020

Reverse Engineering for 2.5-D Split Manufactured ICs.

[BibT_eX]

[DOI]

Yizhang Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Channel Tiling for Improved Performance and Accuracy of Optical Neural Network Accelerators.

[BibT_eX]

[DOI]

CoRR, 2020

Pathfinding for 2.5D interconnect technologies.

[BibT_eX]

[DOI]

Proceedings of the SLIP '20: System-Level Interconnect, 2020

SAME-Infer: Software Assisted Memory Resilience for Efficient Inference at the Edge.

[BibT_eX]

[DOI]

Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Theory, 2019

Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training.

[BibT_eX]

[DOI]

IEEE Micro, 2019

Variability Expeditions: A Retrospective.

[BibT_eX]

[DOI]

Rajesh K. Gupta

Subhasish Mitra

IEEE Des. Test, 2019

Compression with multi-ECC: enhanced error resiliency for magnetic memories.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2019

Architecting Waferscale Processors - A GPU Case Study.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2018

Design and Analysis of Stability-Guaranteed PUFs.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2018

Assessing Layout Density Benefits of Vertical Channel Devices.

[BibT_eX]

[DOI]

Charles Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Implementation and Analysis of Stable PUFs Using Gate Oxide Breakdown.

[BibT_eX]

[DOI]

CoRR, 2018

Error Correction and Detection for Computing Memories Using System Side Information.

[BibT_eX]

[DOI]

Proceedings of the IEEE Information Theory Workshop, 2018

A Case for Packageless Processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Parity++: Lightweight Error Correction for Last Level Caches.

[BibT_eX]

[DOI]

Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2018

2017

A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Low-Cost Memory Fault Tolerance for IoT Devices.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2017

Assessing Benefits of a Buried Interconnect Layer in Digital Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Benchmarking of Mask Fracturing Heuristics.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Mask Assignment and DSA Grouping for DSA-MP Hybrid Lithography for Sub-7 nm Contact/Via Holes.

[BibT_eX]

[DOI]

Yasmine Badr

Andres Torres

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

System-Level Dynamic Variation Margining in Presence of Monitoring and Actuation.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2017

Measuring the Impact of Memory Errors on Application Performance.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2017

Advanced Packaging and Heterogeneous Integration to Reboot Computing.

[BibT_eX]

[DOI]

Subramanian S. Iyer

Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Implementation of stable PUFs using gate oxide breakdown.

[BibT_eX]

[DOI]

Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016

PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

MEMRES: A Fast Memory System Reliability Simulator.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2016

Efficient Layout Generation and Design Evaluation of Vertical Channel Devices.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Comparative Evaluation of Spin-Transfer-Torque and Magnetoelectric Random Access Memory.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

X-Mem: A cross-platform and extensible memory characterization tool for the cloud.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

LEDPUF: Stability-guaranteed physical unclonable functions through locally enhanced defectivity.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Software-Defined Error-Correcting Codes.

[BibT_eX]

[DOI]

Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2016

Multi-story power distribution networks for GPUs.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

MTJ variation monitor-assisted adaptive MRAM write.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Hardware Reliability margining for the dark silicon era.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2015

NSF expedition on variability-aware software: Recent results and contributions.

[BibT_eX]

[DOI]

it Inf. Technol., 2015

Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation.

[BibT_eX]

[DOI]

Santanu Sarma

Nikil D. Dutt

Nalini Venkatasubramanian

Alexandru Nicolau

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Effective model-based mask fracturing for mask cost reduction.

[BibT_eX]

[DOI]

Abde Ali Kagalwalla

Proceedings of the 52nd Annual Design Automation Conference, 2015

Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7nm contacts/vias.

[BibT_eX]

[DOI]

Yasmine Badr

Andres Torres

Proceedings of the 52nd Annual Design Automation Conference, 2015

Evaluating and exploiting impacts of dynamic power management schemes on system reliability.

[BibT_eX]

[DOI]

Vikas Chandra

Proceedings of the 2015 International Conference on Compilers, 2015

2014

Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Statistical timing and power analysis of VLSI considering non-linear dependence.

[BibT_eX]

[DOI]

Integr., 2014

BTI-Gater: An Aging-Resilient Clock Gating Methodology.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Minimizing clock domain crossing in Network on Chip interconnect.

[BibT_eX]

[DOI]

Parag Kulkarni

Rudy Beraha

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Pattern-restricted design at 10nm and beyond.

[BibT_eX]

[DOI]

Yasmine Badr

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Efficient layout generation and evaluation of vertical channel devices.

[BibT_eX]

[DOI]

Nalini Venkatasubramanian

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Benchmarking of mask fracturing heuristics.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A Case for Battery Charging-Aware Power Management and Deferrable Task Scheduling in Smartphones.

[BibT_eX]

[DOI]

Proceedings of the 6th Workshop on Power-Aware Computing and Systems, 2014

Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Multi-Layer Memory Resiliency.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

On-chip self-awareness using Cyberphysical-Systems-on-Chip (CPSoC).

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Accurate and inexpensive performance monitoring for variability-aware systems.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

EUV-CDA: Pattern shift aware critical density analysis for EUV mask layouts.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Comprehensive die-level assessment of design rules and layouts.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Hardware Variability-Aware Duty Cycling for Embedded Sensors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Underdesigned and Opportunistic Computing in Presence of Hardware Variability.

[BibT_eX]

[DOI]

Tajana Simunic Rosing

Mani B. Srivastava

Steven Swanson

Dennis Sylvester

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Layout Decomposition and Legalization for Double-Patterning Technology.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Towards analyzing and improving robustness of software applications to intermittent and permanent faults in hardware.

[BibT_eX]

[DOI]

Ankur Sharma

Joseph Sloan

Salma Elmalaki

Mani B. Srivastava

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

SlackProbe: a low overhead in situ on-line timing slack monitoring methodology.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Role of design in multiple patterning: technology development, design enablement and process control.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Reliable on-chip systems in the nano-era: lessons learnt and future trends.

[BibT_eX]

[DOI]

Mehdi Baradaran Tahoori

Norbert Wehn

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

VarEMU: An emulation testbed for variability-aware software.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

ARGO: Aging-aware GPGPU register file allocation.

[BibT_eX]

[DOI]

Majid Namaki-Shoushtari

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Design for nanoscale patterning.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Variability-aware memory management for nanoscale computing.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

AppAdapt: Opportunistic Application Adaptation in Presence of Hardware Variation.

[BibT_eX]

[DOI]

Aashish Pant

Mihaela van der Schaar

IEEE Trans. Very Large Scale Integr. Syst., 2012

Discrete sizing for leakage power optimization in physical design: A comparative study.

[BibT_eX]

[DOI]

Santiago Mok

ACM Trans. Design Autom. Electr. Syst., 2012

ECO cost measurement and incremental gate sizing for late process changes.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

Design-Aware Mask Inspection.

[BibT_eX]

[DOI]

Abde Ali Kagalwalla

Christopher J. Progler

Steve McDonald

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment.

[BibT_eX]

[DOI]

Found. Trends Electron. Des. Autom., 2012

Power Variability in Contemporary DRAMs.

[BibT_eX]

[DOI]

Mark Gottscho

Abde Ali Kagalwalla

IEEE Embed. Syst. Lett., 2012

Parametric Hierarchy Recovery in Layout Extracted Netlists.

[BibT_eX]

[DOI]

Fedor Pikus

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Impact of range and precision in technology on cell-based design.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

A methodology for the early exploration of design rules for multiple-patterning technologies.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

VaMV: Variability-aware Memory Virtualization.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

ViPZonE: OS-level memory variability-driven physical address zoning for energy savings.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011

Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Trading Accuracy for Power in a Multiplier Architecture.

[BibT_eX]

[DOI]

Parag Kulkarni

Milos D. Ercegovac

J. Low Power Electron., 2011

Trading Accuracy for Power with an Underdesigned Multiplier Architecture.

[BibT_eX]

[DOI]

Parag Kulkarni

Milos D. Ercegovac

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A framework for double patterning-enabled design.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Variability-aware duty cycle scheduling in long running embedded sensing systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

On the efficacy of NBTI mitigation techniques.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Underdesigned and Opportunistic Computing.

[BibT_eX]

[DOI]

Rajesh K. Gupta

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Evaluating Statistical Power Optimization.

[BibT_eX]

[DOI]

Jason Cong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Electrical Modeling of Lithographic Imperfections.

[BibT_eX]

[DOI]

Tuck-Boon Chan

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

On Electrical Modeling of Imperfect Diffusion Patterning.

[BibT_eX]

[DOI]

Tuck-Boon Chan

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Variation-aware speed binning of multi-core processors.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Incremental gate sizing for late process changes.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Computer Design, 2010

Design dependent process monitoring for back-end manufacturing cost reduction.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Software adaptation in quality sensitive applications to deal with hardware variability.

[BibT_eX]

[DOI]

Aashish Pant

Mihaela van der Schaar

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Eyecharts: constructive benchmarking of gate sizing heuristics.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

On confidence in characterization and application of variation models.

[BibT_eX]

[DOI]

Lerong Cheng

Lei He

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Efficient Additive Statistical Leakage Estimation.

[BibT_eX]

[DOI]

Lerong Cheng

Lei He

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A framework for early and systematic evaluation of design rules.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

On the futility of statistical power optimization.

[BibT_eX]

[DOI]

Jason Cong

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Accounting for non-linear dependence using function driven component analysis.

[BibT_eX]

[DOI]

Lerong Cheng

Lei He

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Bounded-lifetime integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Investigation of diffusion rounding for post-lithography analysis.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Detailed Placement for Enhanced Control of Resist and Etch CDs.

[BibT_eX]

[DOI]

Chul-Hong Park

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Line-End Shortening is Not Always a Failure.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

Gate-length biasing for runtime-leakage control.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Wafer Topography-Aware Optical Proximity Correction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Efficient Design and Analysis of Robust Power Distribution Meshes.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Standard cell library optimization for leakage reduction.

[BibT_eX]

[DOI]

Saumil Shah

Proceedings of the 43rd Design Automation Conference, 2006

2005

Routing-aware scan chain ordering.

[BibT_eX]

[DOI]

Stefanus Mantik

ACM Trans. Design Autom. Electr. Syst., 2005

Layout-aware scan chain synthesis for improved path delay fault coverage.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Performance Driven OPC for Mask Cost Reduction.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology.

[BibT_eX]

[DOI]

Puneet Sharma

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Detailed placement for improved depth of focus and CD control.

[BibT_eX]

[DOI]

Chul-Hong Park

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Investigation of performance metrics for interconnect stack architectures.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

Selective gate-length biasing for cost-effective runtime leakage control.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Toward a systematic-variation aware timing methodology.

[BibT_eX]

[DOI]

Fook-Luen Heng

Proceedings of the 41th Design Automation Conference, 2004

Toward a methodology for manufacturability-driven design rule exploration.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2003

A Proposal for Routing-Based Timing-Driven Scan Chain Ordering.

[BibT_eX]

[DOI]

Stefanus Mantik

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Quantifying Error in Dynamic Power Estimation of CMOS Circuits.

[BibT_eX]

[DOI]

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Manufacturing-Aware Physical Design.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A cost-driven lithographic correction methodology based on off-the-shelf sizing tools.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Performance-impact limited area fill synthesis.

[BibT_eX]

[DOI]

Yu Chen