Pui To Lai

According to our database, Pui To Lai authored at least 4 papers between 2009 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2016

Improved interfacial quality of GaAs metal-oxide-semiconductor device with NH₃-plasma treated yittrium-oxynitride as interfacial passivation layer.

Han-Han Lu, Jing-Ping Xu, Lu Liu, Li-Sheng Wang, Pui To Lai, Wing Man Tang

Microelectron. Reliab., 2016

A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric.

Feng Ji, Jing-Ping Xu, Lu Liu, Wing Man Tang, Pui To Lai

Microelectron. Reliab., 2016

2014

Improved performance by using TaON/SiO₂ as dual tunnel layer in Charge-Trapping nonvolatile memory.

J. X. Chen, Jing-Ping Xu, Lu Liu, X. D. Huang, Pui To Lai

Microelectron. Reliab., 2014

2009

A study on the improved programming characteristics of flash memory with Si₃N₄/SiO₂ stacked tunneling dielectric.

Lu Liu, Jing-Ping Xu, L. L. Chen, Pui To Lai

Microelectron. Reliab., 2009