Promod Kumar
According to our database1,
Promod Kumar
authored at least 6 papers
between 2001 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2022
40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
2017
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
2015
FALPEM: Framework for Architectural-Level Power Estimation and Optimization for Large Memory Sub-Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001