Priyank Kalla

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

Design-for-Test for Silicon Photonic Circuits.

[BibT_eX]

[DOI]

Pratishtha Agnihotri

Proceedings of the IEEE International Test Conference, 2024

2023

Abstractions for Modeling the Effects of Wall Surface Roughness in Silicon Photonic Microring Resonators.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Latin American Test Symposium, 2023

Logic Synthesis from Polynomials with Coefficients in the Field of Rationals.

[BibT_eX]

[DOI]

Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023

2021

Algebraic Techniques for Rectification of Finite Field Circuits.

[BibT_eX]

[DOI]

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Word-Level Multi-Fix Rectifiability of Finite Field Arithmetic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Rectification of Integer Arithmetic Circuits using Computer Algebra Techniques.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2019

Boolean Gröbner Basis Reductions on Finite Field Datapath Circuits Using the Unate Cube Set Algebra.

[BibT_eX]

[DOI]

Utkarsh Gupta

Vikas Rao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Exploring Algebraic Interpolants for Rectification of Finite Field Arithmetic Circuits with Gröbner Bases.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE European Test Symposium, 2019

2018

Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018

On the Rectifiability of Arithmetic Circuits using Craig Interpolants in Finite Fields.

[BibT_eX]

[DOI]

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Post-Verification Debugging and Rectification of Finite Field Arithmetic Circuits using Computer Algebra Techniques.

[BibT_eX]

[DOI]

Proceedings of the 2018 Formal Methods in Computer Aided Design, 2018

Emerging Circuit Technologies: An Overview on the Next Generation of Circuits.

[BibT_eX]

[DOI]

Robert Wille

Krishnendu Chakrabarty

Rolf Drechsler

Proceedings of the Advanced Logic Synthesis, 2018

2016

Efficient Symbolic Computation for Word-Level Abstraction From Combinational Circuits for Verification Over Finite Fields.

[BibT_eX]

[DOI]

Tim Pruss

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Methodology for Thermal Characterization Abstraction of Integrated Opto-Electronic Layouts.

[BibT_eX]

[DOI]

Lawrence M. Schlitt

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Word-level traversal of finite state machines using algebraic geometry.

[BibT_eX]

[DOI]

Xiaojun Sun

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

Finding Unsatisfiable Cores of a Set of Polynomials Using the Gröbner Basis Algorithm.

[BibT_eX]

[DOI]

Proceedings of the Principles and Practice of Constraint Programming, 2016

2015

DA Vision 2015: From Here to Eternity.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Formal Verification of Arithmetic Datapaths using Algebraic Geometry and Symbolic Computation.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2015

Formal verification of sequential Galois field arithmetic circuits using algebraic geometry.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Crossing-Aware Channel Routing for Integrated Optics.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Thermal-aware synthesis of integrated photonic ring resonators.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Equivalence Verification of Large Galois Field Arithmetic Circuits using Word-Level Abstraction via Gröbner Bases.

[BibT_eX]

[DOI]

Tim Pruss

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Arithmetic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Channel routing for integrated optics.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

Crossing-aware channel routing for photonic waveguides.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012

Formal Verification of Galois Field Multipliers Using Computer Algebra Techniques.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on VLSI Design, 2012

A methodology for physical design automation for integrated optics.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Efficient Gröbner basis reductions for formal verification of galois field multipliers.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Verification of composite Galois field multipliers over GF ((2<sup>m</sup>)<sup>n</sup>) using computer algebra techniques.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Logic synthesis for integrated optics.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2009

2009 ACM TODAES best paper award: Optimization of polynomial datapaths using finite ring algebra.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Chairs' welcome message.

[BibT_eX]

[DOI]

Prabhat Mishra

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Verification of arithmetic datapaths using polynomial function models and congruence solving.

[BibT_eX]

[DOI]

Neal Tew

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007

Optimization of polynomial datapaths using finite ring algebra.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

A Gröbner Basis Approach to CNF-Formulae Preprocessing.

[BibT_eX]

[DOI]

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2007

Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors.

[BibT_eX]

[DOI]

M. Brandon Meredith

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Optimization of Arithmetic Datapaths with Finite Word-Length Operands.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs.

[BibT_eX]

[DOI]

Serkan Askar

IEEE Trans. Computers, 2006

Guiding CNF-SAT Search by Analyzing Constraint-Variable Dependencies and Clause Lengths.

[BibT_eX]

[DOI]

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006

Equivalence verification of arithmetic datapaths with multiple word-length operands.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Variable Ordering for Efficient SAT Search by Analyzing Constraint-Variable Dependencies.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing, 2005

Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004

Guiding CNF-SAT search via efficient constraint partitioning.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Dynamic analysis of constraint-variable dependencies to guide SAT diagnosis.

[BibT_eX]

[DOI]

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Exploiting hypergraph partitioning for efficient Boolean satisfiability.

[BibT_eX]

[DOI]

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

2003

Integrating CNF and BDD based SAT solvers.

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

2002

BDD-based logic synthesis for LUT-based FPGAs.

[BibT_eX]

[DOI]

Navin Vemuri

Russell Tessier

ACM Trans. Design Autom. Electr. Syst., 2002

A comprehensive approach to the partial scan problem using implicitstate enumeration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

High-level design verification using Taylor Expansion Diagrams: first results.

[BibT_eX]

[DOI]

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

Strategies for solving the Boolean satisfiability problem using binary decision diagrams.

[BibT_eX]

[DOI]

Zhihong Zeng

J. Syst. Archit., 2001

Taylor expansion diagrams: a new representation for RTL verification.

[BibT_eX]

[DOI]

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

LPSAT: a unified approach to RTL satisfiability.

[BibT_eX]

[DOI]

Zhihong Zeng

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

1999

Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

1998

A comprehensive approach to the partial scan problem using implicit state enumeration.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

Testability of Sequential Circuits with Multi-Cycle False Path.

[BibT_eX]

[DOI]