Pritish Narayanan

According to our database, Pritish Narayanan authored at least 50 papers between 2007 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of two.

2023

A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh.

Shubham Jain, Hsinyu Tsai, Ching-Tzu Chen, Ramachandran Muralidhar, Irem Boybat, Martin M. Frank, Stanislaw Wozniak, Milos Stanisavljevic, Praneet Adusumilli, Pritish Narayanan, Kohji Hosokawa, Masatoshi Ishii, Arvind Kumar, Vijay Narayanan, Geoffrey W. Burr

IEEE Trans. Very Large Scale Integr. Syst., 2023

An analog-AI chip for energy-efficient speech recognition and transcription.

Stefano Ambrogio, Pritish Narayanan, Atsuya Okazaki, Andrea Fasoli, Charles Mackin, Kohji Hosokawa, Akiyo Nomura, Takeo Yasuda, An Chen, Alexander M. Friz, Masatoshi Ishii, Jose Luquin, Yasuteru Kohda, Nicole Saulnier, Kevin Brew, Samuel Choi, Injo Ok, Timothy Philip, Victor Chan, Mary Claire Silvestre, Ishtiaq Ahsan, Vijay Narayanan, Hsinyu Tsai, Geoffrey W. Burr

Nat., 2023

Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.

Malte J. Rasch, Charles Mackin, Manuel Le Gallo, An Chen, Andrea Fasoli, Frédéric Odermatt, Ning Li, S. R. Nandakumar, Pritish Narayanan, Hsinyu Tsai, Geoffrey W. Burr, Abu Sebastian, Vijay Narayanan

CoRR, 2023

Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited).

Geoffrey W. Burr, Pritish Narayanan, Stefano Ambrogio, Atsuya Okazaki, Hsinyu Tsai, Kohji Hosokawa, Charles Mackin, Akiyo Nomura, Takeo Yasuda, J. Demarest, Kevin Brew, Victor Chan, Samuel Choi, T. Gordon, T. M. Levin, Alexander M. Friz, Masatoshi Ishii, Yasuteru Kohda, An Chen, Andrea Fasoli, Jose Luquin, Nicole Saulnier, S. Teehan, Ishtiaq Ahsan, Vijay Narayanan

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited).

Hsinyu Tsai, Pritish Narayanan, Shubham Jain, Stefano Ambrogio, Kohji Hosokawa, Masatoshi Ishii, Charles Mackin, Ching-Tzu Chen, Atsuya Okazaki, Akiyo Nomura, Irem Boybat, Ramachandran Muralidhar, Martin M. Frank, Takeo Yasuda, Alexander M. Friz, Yasuteru Kohda, An Chen, Andrea Fasoli, Malte J. Rasch, Stanislaw Wozniak, Jose Luquin, Vijay Narayanan, Geoffrey W. Burr

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited).

Martin M. Frank, Ning Li, Malte J. Rasch, Shubham Jain, Ching-Tzu Chen, Ramachandran Muralidhar, Jin-Ping Han, Vijay Narayanan, Timothy Philip, Kevin Brew, Andrew Simon, Iqbal Saraf, Nicole Saulnier, Irem Boybat, Stanislaw Wozniak, Abu Sebastian, Pritish Narayanan, Charles Mackin, An Chen, Hsinyu Tsai, Geoffrey W. Burr

Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022

Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers.

Atsuya Okazaki, Pritish Narayanan, Stefano Ambrogio, Kohji Hosokawa, Hsinyu Tsai, Akiyo Nomura, Takeo Yasuda, Charles Mackin, Alexander M. Friz, Masatoshi Ishii, Yasuteru Kohda, Katie Spoon, An Chen, Andrea Fasoli, Malte J. Rasch, Geoffrey W. Burr

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices.

Katie Spoon, Hsinyu Tsai, An Chen, Malte J. Rasch, Stefano Ambrogio, Charles Mackin, Andrea Fasoli, Alexander M. Friz, Pritish Narayanan, Milos Stanisavljevic, Geoffrey W. Burr

Frontiers Comput. Neurosci., 2021

Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited).

Kohji Hosokawa, Pritish Narayanan, Stefano Ambrogio, Hsinyu Tsai, Charles Mackin, Andrea Fasoli, Alexander M. Friz, An Chen, Jose Luquin, Katherine Spoon, Geoffrey W. Burr, Scott C. Lewis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

Overview of the IBM Neural Computer Architecture.

Pritish Narayanan, Charles E. Cox, Alexis Asseman, Nicolas Antoine, Harald Huels, Winfried W. Wilcke, Ahmet S. Ozcan

CoRR, 2020

Optimization of Analog Accelerators for Deep Neural Networks Inference.

Andrea Fasoli, Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Charles Mackin, Katherine Spoon, Alexander M. Friz, An Chen, Geoffrey W. Burr

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges.

Charles Mackin, Pritish Narayanan, Stefano Ambrogio, Hsinyu Tsai, Katie Spoon, Andrea Fasoli, An Chen, Alexander M. Friz, Robert M. Shelby, Geoffrey W. Burr

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Accelerating Deep Neural Networks with Analog Memory Devices.

Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Charles Mackin, Katherine Spoon, An Chen, Andrea Fasoli, Alexander M. Friz, Geoffrey W. Burr

Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019

AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed.

Hung-Yang Chang, Pritish Narayanan, Scott C. Lewis, Nathan C. P. Farinha, Kohji Hosokawa, Charles Mackin, Hsinyu Tsai, Stefano Ambrogio, An Chen, Geoffrey W. Burr

IBM J. Res. Dev., 2019

Analog-to-Digital Conversion With Reconfigurable Function Mapping for Neural Networks Activation Function Acceleration.

Massimo Giordano, Giorgio Cristiano, Koji Ishibashi, Stefano Ambrogio, Hsinyu Tsai, Geoffrey W. Burr, Pritish Narayanan

IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Non-filamentary non-volatile memory elements as synapses in neuromorphic systems.

Alessandro Fumarola, Yusuf Leblebici, Pritish Narayanan, Robert M. Shelby, L. L. Sanchez, Geoffrey W. Burr, Kibong Moon, J. Jang, Hyunsang Hwang, Severin Sidler

Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019

2018

Equivalent-accuracy accelerated neural-network training using analogue memory.

Stefano Ambrogio, Pritish Narayanan, Hsinyu Tsai, Robert M. Shelby, Irem Boybat, Carmelo di Nolfo, Severin Sidler, Massimo Giordano, Martina Bodini, Nathan C. P. Farinha, Benjamin Killeen, Christina Cheng, Yassine Jaoudi, Geoffrey W. Burr

Nat., 2018

Panel discussions: "Challenges to the scaling limits: How can we achieve sustainable power-performance improvements?".

Koji Inoue, Takuya Araki, Takumi Maruyama, Pritish Narayanan, Takashi Oshima, Martin Schulz

Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

2017

Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory.

Pritish Narayanan, Alessandro Fumarola, Lucas L. Sanches, Kohji Hosokawa, Scott C. Lewis, Robert M. Shelby, Geoffrey W. Burr

IBM J. Res. Dev., 2017

Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays.

Pritish Narayanan, Lucas L. Sanches, Alessandro Fumarola, Robert M. Shelby, Stefano Ambrogio, Jun-Woo Jang, Hyunsang Hwang, Yusuf Leblebici, Geoffrey W. Burr

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Neuromorphic devices and architectures for next-generation cognitive computing.

Geoffrey W. Burr, Pritish Narayanan, Robert M. Shelby, Stefano Ambrogio, Hsinyu Tsai, Scott L. Lewis, Kohji Hosokawa

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique.

Irem Boybat, Carmelo di Nolfo, Stefano Ambrogio, Martina Bodini, Nathan C. P. Farinha, Robert M. Shelby, Pritish Narayanan, Severin Sidler, Hsinyu Tsai, Yusuf Leblebici, Geoffrey W. Burr

Proceedings of the IEEE International Conference on Rebooting Computing, 2017

2016

Circuit-Level Benchmarking of Access Devices for Resistive Nonvolatile Memory Arrays.

Pritish Narayanan, Geoffrey W. Burr, Kumar Virwani, Bülent N. Kurdi

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Accelerating machine learning with Non-Volatile Memory: Exploring device and circuit tradeoffs.

Alessandro Fumarola, Pritish Narayanan, Lucas L. Sanches, Severin Sidler, Jun-Woo Jang, Kibong Moon, Robert M. Shelby, Hyunsang Hwang, Geoffrey W. Burr

Proceedings of the IEEE International Conference on Rebooting Computing, 2016

Large-scale neural networks implemented with Non-Volatile Memory as the synaptic weight element: Impact of conductance response.

Severin Sidler, Irem Boybat, Robert M. Shelby, Pritish Narayanan, Jun-Woo Jang, Alessandro Fumarola, Kibong Moon, Yusuf Leblebici, Hyunsang Hwang, Geoffrey W. Burr

Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015

Deep Learning with Limited Numerical Precision.

Suyog Gupta, Ankur Agrawal, Kailash Gopalakrishnan, Pritish Narayanan

Proceedings of the 32nd International Conference on Machine Learning, 2015

2014

Parameter variation sensing and estimation in nanoscale fabrics.

Jianfeng Zhang, Mostafizur Rahman, Pritish Narayanan, Santosh Khasanvis, Csaba Andras Moritz

J. Parallel Distributed Comput., 2014

Introduction to JPDC special issue on computing with future nanotechnology.

Csaba Andras Moritz, Santosh Khasanvis, Pritish Narayanan

J. Parallel Distributed Comput., 2014

Metal-Gated Junctionless Nanowire Transistors.

Mostafizur Rahman, Pritish Narayanan, Csaba Andras Moritz

CoRR, 2014

2013

Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation.

Pritish Narayanan, Michael Leuchtenburg, Jorge Kina, Prachi Joshi, Pavan Panchapakeshan, Chi On Chui, Csaba Andras Moritz

ACM J. Emerg. Technol. Comput. Syst., 2013

Experimental prototyping of beyond-CMOS nanowire computing fabrics.

Mostafizur Rahman, Pritish Narayanan, Santosh Khasanvis, John Nicholson, Csaba Andras Moritz

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Nanowire field-programmable computing platform.

Santosh Khasanvis, Mostafizur Rahman, Prasad Shabadi, Pritish Narayanan, Hyung Suk Yu, Chi On Chui, Csaba Andras Moritz

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

2012

Ternary volatile random access memory based on heterogeneous graphene-CMOS fabric.

Santosh Khasanvis, K. M. Masum Habib, Mostafizur Rahman, Pritish Narayanan, Roger K. Lake, Csaba Andras Moritz

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

2011

Energy-Efficient Hardware Data Prefetching.

Yao Guo, Pritish Narayanan, Mahmoud A. Bennaser, Saurabh Chheda, Csaba Andras Moritz

IEEE Trans. Very Large Scale Integr. Syst., 2011

Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics.

Priyamvada Vijayakumar, Pritish Narayanan, Israel Koren, C. Mani Krishna, Csaba Andras Moritz

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Regular 2D NASIC-based architecture and design space exploration.

Ciprian Teodorov, Pritish Narayanan, Loïc Lagadec, Catherine Dezan

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

N3ASICs: Designing nanofabrics with fine-grained CMOS integration.

Pavan Panchapakeshan, Pritish Narayanan, Csaba Andras Moritz

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Nanoscale Application Specific Integrated Circuits.

Pritish Narayanan, Jorge Kina, Pavan Panchapakeshan, Priyamvada Vijayakumar, Kyeong-Sik Shin, Mostafizur Rahman, Michael Leuchtenburg, Israel Koren, Chi On Chui, Csaba Andras Moritz

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Hybrid Graphene Nanoribbon-CMOS tunneling volatile memory fabric.

Santosh Khasanvis, K. M. Masum Habib, Mostafizur Rahman, Pritish Narayanan, Roger K. Lake, Csaba Andras Moritz

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Biased Voting for Improved Yield in Nanoscale Fabrics.

Md. Muwyid U. Khan, Pritish Narayanan, Priyamvada Vijayakumar, Israel Koren, C. Mani Krishna, Csaba Andras Moritz

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010

Programmable cellular architectures at the nanoscale.

Pritish Narayanan, Teng Wang, Csaba Andras Moritz

Nano Commun. Networks, 2010

Towards logic functions as the device.

Prasad Shabadi, Alexander Khitun, Pritish Narayanan, Mingqiang Bao, Israel Koren, Kang L. Wang, Csaba Andras Moritz

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance.

Priyamvada Vijayakumar, Pritish Narayanan, Israel Koren, C. Mani Krishna, Csaba Andras Moritz

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration.

Pritish Narayanan, Michael Leuchtenburg, Jorge Kina, Prachi Joshi, Pavan Panchapakeshan, Chi On Chui, Csaba Andras Moritz

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009

Towards a framework for designing applications onto hybrid nano/CMOS fabrics.

Catherine Dezan, Ciprian Teodorov, Loïc Lagadec, Michael Leuchtenburg, Teng Wang, Pritish Narayanan, Csaba Andras Moritz

Microelectron. J., 2009

Validating cascading of crossbar circuits with an integrated device-circuit exploration.

Pritish Narayanan, Csaba Andras Moritz, Kyoung-won Park, Chi On Chui

Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

2008

Impact of Process Variation in Fault-Resilient Streaming Nanoprocessors.

Michael Leuchtenburg, Pritish Narayanan, Teng Wang, Csaba Andras Moritz

Proceedings of the Nano-Net - Third International ICST Conference, 2008

CMOS Control Enabled Single-Type FET NASIC.

Pritish Narayanan, Michael Leuchtenburg, Teng Wang, Csaba Andras Moritz

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007

Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids.

Csaba Andras Moritz, Teng Wang, Pritish Narayanan, Michael Leuchtenburg, Yao Guo, Catherine Dezan, Mahmoud A. Bennaser

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Combining 2-level logic families in grid-based nanoscale fabrics.

Teng Wang, Pritish Narayanan, Csaba Andras Moritz

Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007