Prem R. Menon

According to our database, Prem R. Menon authored at least 59 papers between 1967 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2006

Design-specific path delay testing in lookup-table-based FPGAs.

Premachandran R. Menon, Weifeng Xu, Russell Tessier

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2001

Identification of primitive faults in combinational and sequentialcircuits.

Ramesh C. Tekumalla, Premachandran R. Menon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

BIST-based delay path testing in FPGA architectures.

Ian G. Harris, Premachandran R. Menon, Russell Tessier

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

On Redundant Path Delay Faults in Synchronous Sequential Circuits.

Ramesh C. Tekumalla, Premachandran R. Menon

IEEE Trans. Computers, 2000

1999

Robust testability of primitive faults using test points.

Ramesh C. Tekumalla, Premachandran R. Menon

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

On primitive fault test generation in non-scan sequential circuits.

Ramesh C. Tekumalla, Premachandran R. Menon

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

Logic optimization and equivalence checking by implication analysis.

Wolfgang Kunz, Dominik Stoffel, Prem R. Menon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Delay Testing with Clock Control: An Alternative to Enhanced Scan.

Ramesh C. Tekumalla, Premachandran R. Menon

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan.

Ramesh C. Tekumalla, Premachandran R. Menon

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Test generation for primitive path delay faults in combinational circuits.

Ramesh C. Tekumalla, Premachandran R. Menon

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Fault simulation on reconfigurable hardware.

Miron Abramovici, Prem R. Menon

Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

1996

Identifying Redundant Path Delay Faults in Sequential Circuits.

Ramesh C. Tekumalla, Premachandran R. Menon

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995

Delay-testable implementations of symmetric functions.

Wuudiann Ke, Premachandran R. Menon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Path-delay-fault testable nonscan sequential circuits.

Wuudiann Ke, Premachandran R. Menon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Synthesis of Delay-Verifiable Combinational Circuits.

Wuudiann Ke, Premachandran R. Menon

IEEE Trans. Computers, 1995

Multifault and delay-fault testability of multilevel circuits.

Wuudiann Ke, Premachandran R. Menon

J. Electron. Test., 1995

Multifault testability of delay-testable circuits.

Wuudiann Ke, Premachandran R. Menon

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

1994

Redundancy identification and removal in combinational circuits.

Prem R. Menon, Hitesh Ahuja, Mohan Harihara

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Realization of fully path-delay-fault testable non-scan sequential circuits.

Wuudiann Ke, Premachandran R. Menon

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Delay-Verifiability of Combinational Circuits Based on Primitive Faults.

Wuudiann Ke, Premachandran R. Menon

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Multi-level logic optimization by implication analysis.

Wolfgang Kunz, Prem R. Menon

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Synthesis of Delay-Verifiable Two-Level Circuits.

Wuudiann Ke, Premachandran R. Menon

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Delay Reduction by Segment Substitution.

Hitesh Ajuha, Premachandran R. Menon

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Divergence and scheduling in functional level concurrent fault simulation.

O. Y. Song, Bong-Hee Park, Prem R. Menon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

3-valued trace-based fault simulation of synchronous sequential circuits.

Ohyoung Song, Premachandran R. Menon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Acceleration of trace-based fault simulation of combinational circuits.

Ohyoung Song, Premachandran R. Menon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992

Redundancy removal and simplification of combinational circuits.

Prem R. Menon, Hitesh Ahuja

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1991

SCRIPT: a critical path tracing algorithm for synchronous sequential circuits.

Premachandran R. Menon, Ytzhak H. Levendel, Miron Abramovici

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Robustly Scan-Testable CMOS Sequential Circuits.

Bong-Hee Park, Premachandran R. Menon

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

Parallel pattern fault simulation based on stem faults in combinational circuits.

Ohyoung Song, Premachandran R. Menon

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Design of scan-testable CMOS sequential circuits.

Bong-Hee Park, Premachandran R. Menon

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989

An Approach to Functional Level Testability Analysis.

C. H. Chen, Premachandran R. Menon

Proceedings of the Proceedings International Test Conference 1989, 1989

Symbolic Test Generation for Hierarchically Modeled Digital Systems.

P. N. Anirudhan, Premachandran R. Menon

Proceedings of the Proceedings International Test Conference 1989, 1989

Identification of undetectable faults in combinational circuits.

Mohan Harihara, Prem R. Menon

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

System-level design verification in the AT&T Computer Division: tools.

Miron Abramovici, James J. Kulikowski, David T. Miller, Prem R. Menon

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988

Critical path tracing in sequential circuits.

Prem R. Menon, Ytzhak H. Levendel, Miron Abramovici

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1986

Checkpoint Faults are not Sufficient Target Faults for Test Generation.

Miron Abramovici, Prem R. Menon, David T. Miller

IEEE Trans. Computers, 1986

SMART and FAST: Test Generation for VLSI Scan-Design Circuits.

Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller

IEEE Des. Test, 1986

1985

A Practical Approach to Fault Simulation and Test Generation for Bridging Faults.

Miron Abramovici, Prem R. Menon

IEEE Trans. Computers, 1985

Test Generation In Lamp2: Concepts and Algorithms.

Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller

Proceedings of the Proceedings International Test Conference 1985, 1985

Test Generation In Lamp2: System Overview.

Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller

Proceedings of the Proceedings International Test Conference 1985, 1985

1984

Critical Path Tracing: An Alternative to Fault Simulation.

Miron Abramovici, Prem R. Menon, David T. Miller

IEEE Des. Test, 1984

1983

A Logic Simulation Machine.

Miron Abramovici, Ytzhak H. Levendel, Premachandran R. Menon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

Totally Preset Checking Experiments for Sequential Machines.

Gordon K. Lin, Premachandran R. Menon

IEEE Trans. Computers, 1983

Parallel fault simulation using distributed processing.

Ytzhak H. Levendel, Prem R. Menon, Suresh H. Patel

Bell Syst. Tech. J., 1983

1982

Test Generation Algorithms for Computer Hardware Description Languages.

Ytzhak H. Levendel, Premachandran R. Menon

IEEE Trans. Computers, 1982

1978

Deductive Fault Simulation with Functional Blocks.

Premachandran R. Menon, Stephen G. Chappell

IEEE Trans. Computers, 1978

1976

Functional simulation in the lamp system.

Stephen G. Chappell, Prem R. Menon, John F. Pellegrin, A. M. Schowe

Proceedings of the 13th Design Automation Conference, 1976

1973

Restricted Checking Sequences for Sequential Machines.

Arthur D. Friedman, Premachandran R. Menon

IEEE Trans. Computers, 1973

1972

Comments on "Design of Diagnosable Iterative Arrays".

Arthur D. Friedman, Prem R. Menon

IEEE Trans. Computers, 1972

1971

Fault Detection in Iterative Logic Arrays.

Premachandran R. Menon, Arthur D. Friedman

IEEE Trans. Computers, 1971

Systems of Asynchronously Operating Modules.

Arthur D. Friedman, Prem R. Menon

IEEE Trans. Computers, 1971

1969

Design of Generalized Double Rank and Multiple Rank Sequential Circuits

Arthur D. Friedman, Prem R. Menon

Inf. Control., November, 1969

On Sequential Machine Decompositions for Reducing the Number of Delay Elements

Premachandran R. Menon

Inf. Control., September, 1969

Structural Simplification and Decomposition of Asynchronous Sequential Circuits.

Chung-Jen Tan, Premachandran R. Menon, Arthur D. Friedman

IEEE Trans. Computers, 1969

Design of Asynchronous Circuits Assuming Unbounded Gate Delays.

Douglas B. Armstrong, Arthur D. Friedman, Premachandran R. Menon

IEEE Trans. Computers, 1969

1968

Synthesis of Asynchronous Sequential Circuits with Multiple-Input Changes.

Arthur D. Friedman, Prem R. Menon

IEEE Trans. Computers, 1968

Realization of Asynchronous Sequential Circuits Without Inserted Delay Elements.

Douglas B. Armstrong, Arthur D. Friedman, Premachandran R. Menon

IEEE Trans. Computers, 1968

1967

Synthesis of Asynchronous Sequential Circuits with Minimum Number of Delay Elements

Douglas B. Armstrong, Arthur D. Friedman, Prem R. Menon

Proceedings of the 8th Annual Symposium on Switching and Automata Theory, 1967