Prawal Shrestha
According to our database1,
Prawal Shrestha
authored at least 5 papers
between 2018 and 2024.
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Bibliography
2024
A -90-dBFS-IM<sub>3</sub>, -164-dBFS/Hz-NSD, 700-MHz-Bandwidth Continuous-Time Pipelined ADC With Digital Cancellation of DAC Errors.
IEEE J. Solid State Circuits, December, 2024
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.
IEEE J. Solid State Circuits, April, 2024
22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2020
16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2018
A -89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2018