Pravinah Nair Shasidharan

According to our database, Pravinah Nair Shasidharan authored at least 4 papers between 2019 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A 919 MHz - 923 MHz, 21 dBm CMOS Power Amplifier With Bias Modulation Linearization Technique Achieving PAE of 29% for LoRa Application.

Arvind Singh Rawat, Jagadheswaran Rajendran, Selvakumar Mariappan, Pravinah Nair Shasidharan, Narendra Kumar, Binboga Siddik Yarman

IEEE Access, 2022

2021

An On-Chip Integrated CMOS Ring Mixer-Balun-VCO Achieving IIP3 of 11.2 dBm and Phase Noise of -117.2 dBc/Hz.

Pravinah Nair Shasidharan, Jagadheswaran Rajendran, Selvakumar Mariappan, Yusman Mohd Yusof

Proceedings of the 11th International Conference on Robotics, Vision, Signal Processing and Power Applications, 2021

2019

A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA.

Zechariah Balan, Harikrishnan Ramiah, Jagadheswaran Rajendran, Nandini Vitee, Pravinah Nair Shasidharan, Jun Yin, Pui-In Mak, Rui Paulo Martins

Integr., 2019

A 2.2 to 2.9 GHz Complementary Class-C VCO With PMOS Tail-Current Source Feedback Achieving - 120 dBc/Hz Phase Noise at 1 MHz Offset.

Pravinah Nair Shasidharan, Harikrishnan Ramiah, Jagadheswaran Rajendran

IEEE Access, 2019