Praveen Raj Ayyappan

Orcid: 0009-0003-9652-430X

According to our database1, Praveen Raj Ayyappan authored at least 5 papers between 2023 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Bibliography

2024
A 65 nm CMOS Analog Programmable Standard Cell Library for Mixed-Signal Computing.
IEEE Trans. Very Large Scale Integr. Syst., October, 2024

A 130nm CMOS Programmable Analog Standard Cell Library.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2024

A 65nm and 130nm CMOS Programmable Analog Standard Cell Library for Scalable System Synthesis.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
Towards Scalable Digital Modeling of Networks of Biorealistic Silicon Neurons.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023

Toward Biorealistic Silicon Neural Circuits on Reconfigurable Platforms.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023


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