Praveen Parvathala

According to our database, Praveen Parvathala authored at least 7 papers between 2002 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation.

Irith Pomeranz, Praveen Parvathala, Srinivas Patil

Proceedings of the 16th Asian Test Symposium, 2007

2006

Session Abstract.

Praveen Parvathala

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests.

Sungchul Park, Li Chen, Praveen Parvathala, Srinivas Patil, Irith Pomeranz

Proceedings of the 2006 IEEE International Test Conference, 2006

A Functional Fault Model with Implicit Fault Effect Propagation Requirements.

Irith Pomeranz, Srinivas Patil, Praveen Parvathala

Proceedings of the 15th Asian Test Symposium, 2006

2005

On Silicon-Based Speed Path Identification.

Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

High Level Test Generation / SW based Embedded Test.

Praveen Parvathala

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2002

FRITS - A Microprocessor Functional BIST Method.

Praveen Parvathala, Kaila Maneparambil, William Lindsay

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002