Praveen Mosalikanti
Orcid: 0009-0002-2948-6289
According to our database1,
Praveen Mosalikanti
authored at least 7 papers
between 2009 and 2024.
Collaborative distances:
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Bibliography
2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2021
29.3 80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with Self- Referenced Asynchronous Adaptive Droop Mitigation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2015
Low power analog circuit techniques in the 5<sup>th</sup> generation intel core<sup>TM</sup> microprocessor (broadwell).
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2011
2009
IEEE J. Solid State Circuits, 2009