Praveen K. Murthy

Proceedings of the 2014 International Test Conference, 2014

2007

Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls.

[BibT_eX]

[DOI]

Ming-Yung Ko

ACM Trans. Embed. Comput. Syst., 2007

2004

The CBP Parameter: A Module Characterization Approach for DSP Software Optimization.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2004

Buffer merging - a powerful technique for reducing memory requirements of synchronous dataflow specifications.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2004

Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition.

[BibT_eX]

[DOI]

Ming-Yung Ko

Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

High level hardware validation using hierarchical message sequence charts.

[BibT_eX]

[DOI]

Sreeranga P. Rajan

Koichiro Takayama

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

2002

Multidimensional synchronous dataflow.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2002

2001

Shared buffer implementations of signal processing systems usinglifetime analysis techniques.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

System canvas: a new design environment for embedded DSP and telecommunication systems.

[BibT_eX]

[DOI]

Etan G. Cohen

Steve Rowland

Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000

The CBP parameter - a useful annotation to aid block-diagram compilers for DSP.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Shared Memory Implementations of Synchronous Dataflow Specifications.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

1999

Synthesis of Embedded Software from Synchronous Dataflow Specifications.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1999

A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on System Synthesis, 1999

1998

Scheduling for Embedded Real-Time Systems.

[BibT_eX]

[DOI]

Felice Balarin

Luciano Lavagno

Alberto L. Sangiovanni-Vincentelli

IEEE Des. Test Comput., 1998

1997

Joint Minimization of Code and Data for Synchronous Dataflow Programs.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 1997

APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 1997

Optimized software synthesis for synchronous dataflow.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996

An extension of multidimensional synchronous dataflow to handle arbitrary sampling lattices.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

1995

Converting graphical DSP programs into memory constrained software prototypes.

[BibT_eX]

[DOI]

Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP '95), 1995

1994

Minimizing memory requirements for chain-structured synchronous dataflow programs.

[BibT_eX]

[DOI]