Pratap Tumkur Renukaswamy
Orcid: 0000-0003-4148-7188
According to our database1,
Pratap Tumkur Renukaswamy
authored at least 8 papers
between 2019 and 2024.
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Bibliography
2024
IEEE J. Solid State Circuits, June, 2024
A Single-Channel, 1-GS/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ/conv.-step, Ringamp-Based Pipelined ADC with Background Calibration in 16nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2021
Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth.
IEEE J. Solid State Circuits, 2020
17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019