Prashant J. Nair

Orcid: 0000-0002-1732-4314

Affiliations:
  • University of British Columbia (UBC), Systems and Architectures (STAR) Lab, Vancouver, BC, Canada
  • Quantum Algorithms Institute (QAI), Surrey, BC, Canada
  • Georgia Institute of Technology, Atlanta, GA, USA (PhD 2017)


According to our database1, Prashant J. Nair authored at least 52 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Workload-Aware Hardware Accelerator Mining for Distributed Deep Learning Training.
CoRR, 2024

Accelerating Recommender Model Training by Dynamically Skipping Stale Embeddings.
CoRR, 2024

Keyformer: KV Cache reduction through key tokens selection for Efficient Generative Inference.
Proceedings of the Seventh Annual Conference on Machine Learning and Systems, 2024

A Case for Speculative Address Translation with Rapid Validation for GPUs.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

Qoncord: A Multi-Device Job Scheduling Framework for Variational Quantum Algorithms.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

Heterogeneous Acceleration Pipeline for Recommendation System Training.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

Understanding Mixed Precision GEMM with MPGemmFI: Insights into Fault Resilience.
Proceedings of the IEEE International Conference on Cluster Computing, 2024

Red-QAOA: Efficient Variational Optimization through Circuit Reduction.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
MPGemmFI: A Fault Injection Technique for Mixed Precision GEMM in ML Applications.
CoRR, 2023

Ad-Rec: Advanced Feature Interactions to Address Covariate-Shifts in Recommendation Networks.
CoRR, 2023

Enabling Scalable VQE Simulation on Leading HPC Systems.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Structural Coding: A Low-Cost Scheme to Protect CNNs from Large-Granularity Memory Faults.
Proceedings of the International Conference for High Performance Computing, 2023

FLuID: Mitigating Stragglers in Federated Learning using Invariant Dropout.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

HuffDuff: Stealing Pruned DNNs from Sparse Accelerators.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

SparseFT: Sparsity-aware Fault Tolerance for Reliable CNN Inference on GPUs.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022
The Dirty Secret of SSDs: Embodied Carbon.
CoRR, 2022

TQSim: A Case for Reuse-Focused Tree-Based Quantum Circuit Simulation.
CoRR, 2022

AQUA: Scalable Rowhammer Mitigation by Quarantining Aggressor Rows at Runtime.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Hydra: enabling low-overhead mitigation of row-hammer at ultra-low thresholds via hybrid tracking.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

Randomized row-swap: mitigating Row Hammer by breaking spatial correlation between aggressor and victim rows.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021
Accelerating Recommendation System Training by Leveraging Popular Choices.
Proc. VLDB Endow., 2021

High-Performance Training by Exploiting Hot-Embeddings in Recommendation Systems.
CoRR, 2021

A Case for Emerging Memories in DNN Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
ADAM: Adaptive Block Placement with Metadata Embedding for Hybrid Caches.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2DCC: Cache Compression in Two Dimensions.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Thesaurus: Efficient Cache Compression via Dynamic Clustering.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

A Case for Multi-Programming Quantum Computers.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

2018
LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency.
CoRR, 2018

Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Architectural techniques to enable reliable and scalable memory systems.
PhD thesis, 2017

Architectural Techniques to Enable Reliable and Scalable Memory Systems.
CoRR, 2017

Taming the instruction bandwidth of quantum computers via hardware-managed error correction.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

DICE: Compressing DRAM Caches for Bandwidth and Capacity.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

2016
Citadel: Efficiently Protecting Stacked Memory from TSV and Large Granularity Failures.
ACM Trans. Archit. Code Optim., 2016

FaultSim: A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems.
ACM Trans. Archit. Code Optim., 2016

XED: Exposing On-Die Error Detection Information for Strong Memory Reliability.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
Architectural Support for Mitigating Row Hammering in DRAM Memories.
IEEE Comput. Archit. Lett., 2015

Reducing read latency of phase change memory via early read and Turbo Read.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems.
Proceedings of the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2015

Reducing Refresh Power in Mobile Devices with Morphable ECC.
Proceedings of the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2015

DEUCE: Write-Efficient Encryption for Non-Volatile Memories.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014
Refresh pausing in DRAM memory systems.
ACM Trans. Archit. Code Optim., 2014

Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

2013
ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

A case for Refresh Pausing in DRAM memory systems.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013


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