Prashant Dubey

According to our database1, Prashant Dubey authored at least 10 papers between 2006 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2017
A 0.42V high bandwidth synthesizable parallel access smart memory fabric for computer vision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2014
A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013
PODIA: Power Optimization through Differential Imbalanced Amplifier.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

38dB Tuning Range Coupled VCO Based Divider Architecture with 68uW Power @2.0 GHz in 65nm CMOS.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2010
Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time.
J. Electron. Test., 2010

2008
On Chip Jitter Measurement through a High Accuracy TDC.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

GALS Based Shared Test Architecture for Embedded Memories.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Built in Defect Prognosis for Embedded Memories.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006


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