Prashant Agrawal

According to our database1, Prashant Agrawal authored at least 28 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Traceable mixnets.
Proc. Priv. Enhancing Technol., 2024

YouChoose: A Lightweight Anonymous Proof of Account Ownership.
IACR Cryptol. ePrint Arch., 2024

MultiSiam: A Multiple Input Siamese Network For Social Media Text Classification And Duplicate Text Detection.
CoRR, 2024

Publicly Auditable Privacy-Preserving Electoral Rolls.
Proceedings of the 37th IEEE Computer Security Foundations Symposium, 2024

2023
OpenVoting: Recoverability from Failures in Dual Voting.
IACR Cryptol. ePrint Arch., 2023

Traceable mixnets.
IACR Cryptol. ePrint Arch., 2023

Traceable mixnets.
CoRR, 2023

OpenVoting: Recoverability from Failures in Dual Voting.
Proceedings of the Electronic Voting: 8th International Joint Conference, 2023

2020
An operational architecture for privacy-by-design in public service applications.
CoRR, 2020

2019
A universally verifiable, software independent, bare-handed voting protocol.
CoRR, 2019

2016
Data Flow Transformation for Energy-Efficient Implementation of Givens Rotation-Based QRD.
ACM Trans. Embed. Comput. Syst., 2016

Characterization of VNIR Hyperspectral Sensors with Monolithically Integrated Optical Filters.
Proceedings of the Image Sensors and Imaging Systems 2016, 2016

2014
System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform.
IEEE Embed. Syst. Lett., 2014

Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Energy efficient data flow transformation for Givens Rotation based QR Decomposition.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Data memory optimization in LTE downlink.
Proceedings of the IEEE International Conference on Acoustics, 2013

Memristor-Based (ReRAM) Data Memory Architecture in ASIP Design.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Early exploration for platform architecture instantiation with multi-mode application partitioning.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Partitioning and Assignment Exploration for Multiple Modes of IEEE 802.11n Modem on Heterogeneous MPSoC Platforms.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Beamforming for interference mitigation and its implementation on an SDR baseband processor.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

High level analysis of trade-offs across different partitioning schemes for wireless applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

2009
Performance optimizations for distributed real-time text indexing.
Proceedings of the 16th International Conference on High Performance Computing, 2009

2008
Optimization of BLAS on the Cell Processor.
Proceedings of the High Performance Computing, 2008

2007
A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

An Approach for Pre-Silicon Power Modeling.
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

A path based modeling approach for dynamic power estimation.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2005
Effect of routing convergence time on lightpath establishment in GMPLS-controlled WDM optical networks.
Proceedings of IEEE International Conference on Communications, 2005

2003
A lightweight protocol for wireless sensor networks.
Proceedings of the 2003 IEEE Wireless Communications and Networking, 2003


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