Pranose J. Edavoor

Orcid: 0000-0002-2133-7126

According to our database1, Pranose J. Edavoor authored at least 21 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks.
IEEE Trans. Very Large Scale Integr. Syst., April, 2024

A SIMD Dynamic Fixed Point Processing Engine for DNN Accelerators.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023
Power-Efficient VLSI Architecture of a New Class of Dyadic Gabor Wavelets for Medical Image Retrieval.
IEEE Trans. Very Large Scale Integr. Syst., 2023

Design and Analysis of Posit Quire Processing Engine for Neural Network Applications.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2022
A New Approach to the Design and Implementation of a Family of Multiplier Free Orthogonal Wavelet Filter Banks.
IEEE Trans. Circuits Syst. Video Technol., 2022

A Novel Design of Symmetric Daub-4 Wavelet Filter Bank for Image Analysis.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Novel 4: 2 Approximate Compressor Designs for Multimedia and Neural Network Applications.
J. Circuits Syst. Comput., 2021

A Novel Design of Dyadic db3 Orthogonal Wavelet Filter Bank for Feature Extraction.
Circuits Syst. Signal Process., 2021

Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic.
IEEE Access, 2021

2020
Design and implementation of image kernels using reversible logic gates.
IET Image Process., 2020

An Approximate Low-Power Lifting Scheme Using Reversible Logic.
IEEE Access, 2020

Approximate Multiplier Design Using Novel Dual-Stage 4: 2 Compressors.
IEEE Access, 2020

Reversible Logic Implementation of Image Denoising for Grayscale Images.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019
Design and implementation of a novel low complexity symmetric orthogonal wavelet filter-bank.
IET Image Process., 2019

2018
Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter.
Proceedings of the TENCON 2018, 2018

2017
Implementation of adaptive image compression algorithm using varying bit-length daubechies wavelet coefficient with three-level encryption on Zynq 7000.
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA.
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

2016
FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images.
Proceedings of the 7th International Conference on Computing Communication and Networking Technologies, 2016

2015
Poster: An Efficient Low Power & High Performance in MPSOC.
Proceedings of the Third International Symposium on Women in Computing and Informatics, 2015

An efficient approach for design and testing of FPGA programming using Lab VIEW.
Proceedings of the 2015 International Conference on Advances in Computing, 2015


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