Pranjal Jain
Orcid: 0000-0003-0204-0092
According to our database1,
Pranjal Jain
authored at least 16 papers
between 2009 and 2023.
Collaborative distances:
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Bibliography
2023
Proceedings of the Extended Abstracts of the 2023 CHI Conference on Human Factors in Computing Systems, 2023
Proceedings of the Extended Abstracts of the 2023 CHI Conference on Human Factors in Computing Systems, 2023
Proceedings of the Extended Abstracts of the 2023 CHI Conference on Human Factors in Computing Systems, 2023
2022
Lerna: transformer architectures for configuring error correction tools for short- and long-read genome sequencing.
BMC Bioinform., 2022
Proceedings of the CHI '22: CHI Conference on Human Factors in Computing Systems, New Orleans, LA, USA, 29 April 2022, 2022
Platformisation of Digital Financial Services (DFS): The Journey of DFS in the Global North and Global South.
Proceedings of the CHI '22: CHI Conference on Human Factors in Computing Systems, New Orleans, LA, USA, 29 April 2022, 2022
Proceedings of the CHI '22: CHI Conference on Human Factors in Computing Systems, New Orleans, LA, USA, 29 April 2022, 2022
2021
Simultaneous learning of individual microRNA-gene interactions and regulatory comodules.
BMC Bioinform., 2021
"Who is protecting us? No one!" Vulnerabilities Experienced by Low-Income Indian Merchants Using Digital Payments.
Proceedings of the COMPASS '21: ACM SIGCAS Conference on Computing and Sustainable Societies, Virtual Event, Australia, 28 June 2021, 2021
Proceedings of the CHI '21: CHI Conference on Human Factors in Computing Systems, 2021
From the Margins to the Centre: Defining New Mission and Vision for HCI Research in South Asia.
Proceedings of the CHI '21: CHI Conference on Human Factors in Computing Systems, 2021
2020
Proceedings of the Extended Abstracts of the 2020 CHI Conference on Human Factors in Computing Systems, 2020
2015
Proceedings of the 2015 IEEE International Conference on Industrial Engineering and Engineering Management, 2015
2014
Proceedings of the Intelligent Robots and Computer Vision XXXI: Algorithms and Techniques, 2014
2009
Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology.
Proceedings of the 2009 IEEE International Conference on Electro/Information Technology, 2009