Praneeth Narayanasetti

According to our database, Praneeth Narayanasetti authored at least 3 papers between 2013 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2016

Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes.

Seung Chul Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, Joseph Wang, G. Nallapati, Mustafa Badaroglu, Praneeth Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015

Holistic technology optimization and key enablers for 7nm mobile SoC.

Seung Chul Song, J. Xu, N. N. Mojumder, K. Rim, D. Yang, Jerry Bao, J. Zhu, Joseph Wang, Mustafa Badaroglu, V. Machkaoutsan, Praneeth Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap

Proceedings of the Symposium on VLSI Circuits, 2015

2013

Optimization processing unit (OPU) applied to integrated circuit design and manufacturing.

Don Chih-Liang Chen, Jiann-Tyng Tzeng, David Barry Scott, Shih Wei Peng, Meng-Hung Shen, Kam Tou Sio, Praneeth Narayanasetti

Proceedings of the 2013 IEEE International Conference on Automation Science and Engineering, 2013