Pranav Ashar

According to our database, Pranav Ashar authored at least 63 papers between 1988 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Closing the Verification Gap with Static Sign-off.

Pranav Ashar, Vinod Viswanath

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

2017

Failures and verification solutions related to untimed paths in SOCs.

Pranav Ashar, Vikas Sachdeva, Vinod Viswanath

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2016

A paradigm shift in verification methodology.

Pranav Ashar

Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

2013

Static verification based signoff - A key enabler for managing verification complexity in the modern soc.

Pranav Ashar

Proceedings of the Formal Methods in Computer-Aided Design, 2013

2010

Clock domain verification challenges and scalable solutions.

Pranav Ashar

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

2008

Efficient SAT-based bounded model checking for software verification.

Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Pranav Ashar

Theor. Comput. Sci., 2008

Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking.

Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2006

Efficient distributed SAT and SAT-based distributed Bounded Model Checking.

Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar

Int. J. Softw. Tools Technol. Transf., 2006

Panel: Assertion-Based Verification -What's the Big Deal?

Sandeep K. Shukla, Alan J. Hu, Jacob Abrahams, Pranav Ashar, Harry Foster, Avner Landver, Carl Pixley

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005

Lazy Constraints and SAT Heuristics for Proof-Based Abstraction.

Aarti Gupta, Malay K. Ganai, Pranav Ashar

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

<i>DiVer</i>: SAT-Based Model Checking Platform for Verifying Large Scale Systems.

Malay K. Ganai, Aarti Gupta, Pranav Ashar

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2005

Verification of Embedded Memory Systems using Efficient Memory Modeling.

Malay K. Ganai, Aarti Gupta, Pranav Ashar

Proceedings of the 2005 Design, 2005

Beyond safety: customized SAT-based model checking.

Malay K. Ganai, Aarti Gupta, Pranav Ashar

Proceedings of the 42nd Design Automation Conference, 2005

F-Soft: Software Verification Platform.

Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar

Proceedings of the Computer Aided Verification, 17th International Conference, 2005

2004

Efficient SAT-based unbounded symbolic model checking using circuit cofactoring.

Malay K. Ganai, Aarti Gupta, Pranav Ashar

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Efficient Modeling of Embedded Memories in Bounded Model Checking.

Malay K. Ganai, Aarti Gupta, Pranav Ashar

Proceedings of the Computer Aided Verification, 16th International Conference, 2004

2003

Iterative Abstraction using SAT-based BMC with Proof Analysis.

Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Learning from BDDs in SAT-based bounded model checking.

Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar

Proceedings of the 40th Design Automation Conference, 2003

Abstraction and BDDs Complement SAT-Based BMC in DiVer.

Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar

Proceedings of the Computer Aided Verification, 15th International Conference, 2003

2002

Functional vector generation for sequential HDL models under an observability-based code coverage metric.

Farzan Fallah, Pranav Ashar, Srinivas Devadas

IEEE Trans. Very Large Scale Integr. Syst., 2002

Property-Specific Testbench Generation for Guided Simulation.

Aarti Gupta, Albert E. Casavant, Pranav Ashar, Sean Liu, Akira Mukaiyama, Kazutoshi Wakabayashi

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver.

Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik

Proceedings of the 39th Design Automation Conference, 2002

A fast, inexpensive and scalable hardware acceleration technique for functional simulation.

Srihari Cadambi, Chandra Mulpuri, Pranav Ashar

Proceedings of the 39th Design Automation Conference, 2002

2001

Using complete-1-distinguishability for FSM equivalence checking.

Pranav Ashar, Aarti Gupta, Sharad Malik

ACM Trans. Design Autom. Electr. Syst., 2001

Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs.

Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Property-specific witness graph generation for guided simulation.

Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation.

Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav Ashar

Proceedings of the 38th Design Automation Conference, 2001

2000

An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking.

Zhen Luo, Margaret Martonosi, Pranav Ashar

VLSI Design, 2000

Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture.

Yang Xia, Pranav Ashar

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Fast Error Diagnosis for Combinational Verification.

Aarti Gupta, Pranav Ashar

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

SAT-Based Image Computation with Application in Reachability Analysis.

Aarti Gupta, Zijiang Yang, Pranav Ashar, Anubhav Gupta

Proceedings of the Formal Methods in Computer-Aided Design, Third International Conference, 2000

1999

Using configurable computing to accelerate Boolean satisfiability.

Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation.

Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya

Proceedings of the IEEE International Conference On Computer Design, 1999

An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking.

Zhen Luo, Margaret Martonosi, Pranav Ashar

Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage.

Farzan Fallah, Pranav Ashar, Srinivas Devadas

Proceedings of the 36th Conference on Design Automation, 1999

Exploiting Retiming in a Guided Simulation Based Validation Methodology.

Aarti Gupta, Pranav Ashar, Sharad Malik

Proceedings of the Correct Hardware Design and Verification Methods, 1999

1998

Guarded evaluation: pushing power management to logic synthesis/design.

Vivek Tiwari, Sharad Malik, Pranav Ashar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking.

Aarti Gupta, Pranav Ashar

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Verification of RTL generated from scheduled behavior in a high-level synthesis flow.

Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Solving Boolean Satisfiability with Dynamic Hardware Configurations.

Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik

Proceedings of the Field-Programmable Logic and Applications, 1998

Accelerating Boolean Satisfiability with Configurable Hardware.

Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik

Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability.

Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi

Proceedings of the 35th Conference on Design Automation, 1998

1997

Toward Formalizing a Validation Methodology Using Simulation Coverage.

Aarti Gupta, Sharad Malik, Pranav Ashar

Proceedings of the 34st Conference on Design Automation, 1997

1996

Technology mapping for low power in logic synthesis.

Vivek Tiwari, Pranav Ashar, Sharad Malik

Integr., 1996

Scheduling Techniques to Enable Power Management.

José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar

Proceedings of the 33st Conference on Design Automation, 1996

1995

Test generation for cyclic combinational circuits.

Anand Raghunathan, Pranav Ashar, Sharad Malik

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Functional timing analysis using ATPG.

Pranav Ashar, Sharad Malik

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Exploiting multicycle false paths in the performance optimization of sequential logic circuits.

Pranav Ashar, Sujit Dey, Sharad Malik

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Fast functional simulation using branching programs.

Pranav Ashar, Sharad Malik

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994

Efficient breadth-first manipulation of binary decision diagrams.

Pranav Ashar, Matthew Cheong

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications.

Pranav Ashar, Sharad Malik

Proceedings of the 31st Conference on Design Automation, 1994

1993

Path-delay-fault testability properties of multiplexor-based networks.

Pranav Ashar, Srinivas Devadas, Kurt Keutzer

Integr., 1993

Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks.

Pranav Ashar, Srinivas Devadas, Kurt Keutzer

Formal Methods Syst. Des., 1993

Technology Mapping for Lower Power.

Vivek Tiwari, Pranav Ashar, Sharad Malik

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Boolean satisfiability and equivalence checking using general Binary Decision Diagrams.

Pranav Ashar, Abhijit Ghosh, Srinivas Devadas

Integr., 1992

Exploiting multi-cycle false paths in the performance optimization of sequential circuits.

Pranav Ashar, Sujit Dey, Sharad Malik

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991

Irredundant interacting sequential machines via optimal logic synthesis.

Pranav Ashar, Srinivas Devadas, A. Richard Newton

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Optimum and heuristic algorithms for an approach to finite state machine decomposition.

Pranav Ashar, Srinivas Devadas, A. Richard Newton

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

1990

Testability driven synthesis of interacting finite state machines.

Pranav Ashar, Srinivas Devadas, A. Richard Newton

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test.

Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines.

Pranav Ashar, Srinivas Devadas, A. Richard Newton

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

Optimum and heuristic algorithms for finite state machine decomposition and partitioning.

Pranav Ashar, Srinivas Devadas, A. Richard Newton

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988

Magnitude locked loop.

K. Radhakrishna Rao, Pranav Ashar

Proc. IEEE, 1988