Prakash Mohan Peranandam

According to our database1, Prakash Mohan Peranandam authored at least 14 papers between 2003 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2022
Automatic development of requirement linking matrix based on semantic similarity for robust software development.
J. Syst. Softw., 2022

2019
An MBSE Approach for Development of Resilient Automated Automotive Systems.
Syst., 2019

2012
Efficient coverage of parallel and hierarchical stateflow models for test case generation.
Softw. Test. Verification Reliab., 2012

SmartTestGen+: A Test Suite Booster for Enhanced Structural Coverage.
Proceedings of the Theoretical Aspects of Computing - ICTAC 2012, 2012

An integrated test generation tool for enhanced coverage of Simulink/Stateflow models.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2007
Grid Based Fast Falsification For Bounded Property Checking.
Proceedings of the Forum on specification and Design Languages, 2007

2006
Efficient system traversal and property verification by exploiting circuit locality.
PhD thesis, 2006

Fast falsification based on symbolic bounded property checking.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Distributed Symbolic Bounded Property Checking.
Proceedings of the 4th International Workshop on Parallel and Distributed Methods in Verification, 2005

Overlap reduction in symbolic system traversal.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

2004
Transactional Level Verification and Coverage Metrics by Means of Symbolic Simulation.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Dynamic guiding of bounded property checking.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

2003
Bounded Property Checking with Symbolic Simulation.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

Using Symbolic Simulation for Bounded Property Checking.
Proceedings of the Forum on specification and Design Languages, 2003


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