Pradip Bose
Orcid: 0000-0002-1380-5671
According to our database1,
Pradip Bose
authored at least 202 papers
between 1982 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2007, "For contributions to power modeling and processor design".
Timeline
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On csauthors.net:
Bibliography
2024
Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures.
CoRR, 2024
IEEE Comput. Archit. Lett., 2024
A 400-ns-Settling- Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024
2023
IEEE Trans. Computers, March, 2023
IEEE Comput. Archit. Lett., 2023
Proceedings of the Computer Security - ESORICS 2023, 2023
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
2022
HE-PEx: Efficient Machine Learning under Homomorphic Encryption using Pruning, Permutation and Expansion.
CoRR, 2022
CoRR, 2022
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
Erratum to "Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption.
IEEE Trans. Computers, 2021
The POWER Processor Family: A Historical Perspective From the Viewpoint of Presilicon Modeling.
IEEE Micro, 2021
IEEE Comput. Archit. Lett., 2021
IEEE Comput. Archit. Lett., 2021
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2021
2020
STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors.
CoRR, 2020
Asymmetric Resilience: Exploiting Task-Level Idempotency for Transient Error Recovery in Accelerator-Based Systems.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 2018 IEEE Intelligent Vehicles Symposium, 2018
Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
IBM J. Res. Dev., 2017
IEEE Comput. Archit. Lett., 2017
Invited paper: Secure swarm intelligence: A new approach to many-core power management.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the International Conference on Supercomputing, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
2016
J. Comput. Syst. Sci., 2016
Computer, 2016
Proceedings of the International Conference for High Performance Computing, 2016
Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Resilience characterization of a vision analytics application under varying degrees of approximation.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016
Characterization and mitigation of power contention across multiprogrammed workloads.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016
Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
IBM J. Res. Dev., 2015
Proceedings of the International Conference for High Performance Computing, 2015
Proceedings of the 48th International Symposium on Microarchitecture, 2015
Experience report: An application-specific checkpointing technique for minimizing checkpoint corruption.
Proceedings of the 26th IEEE International Symposium on Software Reliability Engineering, 2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Quantifying sources of error in McPAT and potential impacts on architectural studies.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
2014
ACM Trans. Parallel Comput., 2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Understanding Soft Error Resiliency of Blue Gene/Q Compute Chip through Hardware Proton Irradiation and Software Fault Injection.
Proceedings of the International Conference for High Performance Computing, 2014
Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
Proceedings of the 2014 International Test Conference, 2014
Empirically derived abstractions in uncore power modeling for a server-class processor chip.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Characterization of transient error tolerance for a class of mobile embedded applications.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
2013
Application-level power and performance characterization and optimization on IBM Blue Gene/Q systems.
IBM J. Res. Dev., 2013
Crank it up or dial it down: coordinated multiprocessor frequency and folding control.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
Keynote address thursday: Efficient resilience in future systems: Design and modeling challenges.
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013
2012
Proceedings of the BuildSys '12 Proceedings of the Fourth ACM Workshop on Embedded Sensing Systems for Energy-Efficiency in Buildings, 2012
Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
IEEE Micro, 2011
IEEE Micro, 2011
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Curbing energy cravings in networks: A cross-sectional view across the micro-macro boundary.
Proceedings of the NOCS 2011, 2011
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011
2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the Computer Architecture, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 7th Conference on Computing Frontiers, 2010
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
2009
IEEE Des. Test Comput., 2009
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
2008
IBM J. Res. Dev., 2008
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008
A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Introduction to the special issue on the 2006 reconfigurable and adaptive architecture workshop.
SIGARCH Comput. Archit. News, 2007
Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements.
IEEE J. Solid State Circuits, 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
2006
IEEE Micro, 2006
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006
2005
IEEE Micro, 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005
2004
IEEE Trans. Computers, 2004
SIGMETRICS Perform. Evaluation Rev., 2004
IEEE Micro, 2004
IEEE Micro, 2004
IEEE Micro, 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004
Proceedings of the 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June, 2004
2003
IEEE Micro, 2003
IEEE Micro, 2003
New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors.
IBM J. Res. Dev., 2003
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003
2002
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002
2001
A circuit level implementation of an adaptive issue queue for power-aware microprocessors.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
Ensuring Dependable Processor Performance: An Experience Report on Pre-Silicon Performance Validation.
Proceedings of the 2001 International Conference on Dependable Systems and Networks (DSN 2001) (formerly: FTCS), 2001
2000
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.
IEEE Micro, 2000
Testing for Function and Performance: Towards an Integrated Processor Validation Methodology.
J. Electron. Test., 2000
Simulation and analysis in the small: the case for simple models, metrics and microbenchmarks in computer architecture teaching and research.
Proceedings of the 2000 workshop on Computer architecture education, 2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000
1999
IEEE Micro, 1999
J. Syst. Archit., 1999
Proceedings of the 1999 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 1999
Proceedings of the IEEE International Performance Computing and Communications Conference, 1999
1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
1997
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997
1996
Proceedings of the 1996 workshop on Computer architecture education, 1996
Proceedings of the Second International Symposium on High-Performance Computer Architecture, 1996
1995
Proceedings of the 1995 Workshop on Computer Architecture Education, 1995
1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Proceedings of the Digest of Papers: FTCS/24, 1994
1993
Proceedings of the Sixth International Conference on VLSI Design, 1993
1992
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
1990
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990
1988
A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem.
IEEE Trans. Computers, 1988
Proceedings of the 2nd international conference on Supercomputing, 1988
Heuristic Rule-Based Program Transformations for Enhanced Vectorization.
Proceedings of the International Conference on Parallel Processing, 1988
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988
Proceedings of the VLSI Algorithms and Architectures, 3rd Aegean Workshop on Computing, 1988
1986
Optimal Code Generation for Expressions on Super Scalar Machines.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986
1984
Proceedings of the 11th Annual Symposium on Computer Architecture, 1984
1983
1982
Proceedings of the 19th Design Automation Conference, 1982
Proceedings of the 20th Annual Southeast Regional Conference, 1982