Pradeep Golconda

According to our database1, Pradeep Golconda authored at least 8 papers between 2004 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2007
Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Novel Adaptive Body Biasing Techniques for Energy Efficient Subthreshold CMOS Circuits.
J. Low Power Electron., 2007

A Low Power Domino with Differential-Controlled-Keeper.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005
A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Noise-tolerant high fan-in dynamic CMOS circuit design.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004
A Double-Edge Implicit-Pulsed Level Convert Flip-Flop.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Contention reduced/conditional discharge flip-flops for level conversion in CVS systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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