Pradeep Fernando

According to our database1, Pradeep Fernando authored at least 14 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Blizzard: Adding True Persistence to Main Memory Data Structures.
CoRR, 2023

2021
Adding Persistence to Main Memory Programming.
PhD thesis, 2021

Scheduling HPC Workflows with Intel Optane Persistent Memory.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021

2020
Persistence and Synchronization: Friends or Foes?
CoRR, 2020

2018
NVStream: accelerating HPC workflows with NVRAM-based transport for streaming objects.
Proceedings of the 27th International Symposium on High-Performance Parallel and Distributed Computing, 2018

2017
UNITY: Unified Memory and File Space.
Proceedings of the 7th International Workshop on Runtime and Operating Systems for Supercomputers, 2017

Sparkle: optimizing spark for large memory machines and analytics.
Proceedings of the 2017 Symposium on Cloud Computing, SoCC 2017, Santa Clara, CA, USA, 2017

2016
Phoenix: Memory Speed HPC I/O with NVM.
Proceedings of the 23rd IEEE International Conference on High Performance Computing, 2016

2014
RoboGen: Robot Generation through Artificial Evolution.
Proceedings of the Fourteenth International Conference on the Simulation and Synthesis of Living Systems, 2014

2010
Customizable FPGA IP Core Implementation of a General-Purpose Genetic Algorithm Engine.
IEEE Trans. Evol. Comput., 2010

2008
An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2008

Self-Reconfigurable Analog Array Integrated Circuit Architecture for Space Applications.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008


  Loading...