Pradeep Dhadda
According to our database1,
Pradeep Dhadda
authored at least 2 papers
between 2014 and 2015.
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Bibliography
2015
A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process.
IEEE J. Solid State Circuits, 2015
2014
A 600µA 32 kHz input 960 MHz output CP-PLL with 530ps integrated jitter in 28nm FD-SOI process.
Proceedings of the ESSCIRC 2014, 2014