Prabir Saha

Orcid: 0000-0001-6140-4680

According to our database1, Prabir Saha authored at least 17 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Design of a Novel Inexact 4:2 Compressor and Its Placement in the Partial Product Array for Area, Delay, and Power-Efficient Approximate Multipliers.
Circuits Syst. Signal Process., June, 2024

Inexact radix-4 Booth multipliers based on new partial product generation scheme for image multiplication.
Integr., January, 2024

2022
Minimizing Ancilla Inputs and Garbage Outputs of Reversible BCD Multiplier.
J. Circuits Syst. Comput., 2022

2021
Improved Signed Binary Multiplier Through New Partial Product Generation Scheme.
J. Circuits Syst. Comput., 2021

Design and Analysis of Inexact 3: 2 Compressor-based Radix-4 Multiplier towards Image Multiplication.
Proceedings of the 12th International Conference on Computing Communication and Networking Technologies, 2021

2020
New design approaches of reversible BCD encoder using Peres and Feynman gates.
ICT Express, 2020

A Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder.
Period. Polytech. Electr. Eng. Comput. Sci., 2020

Modeling of Short P-Channel Symmetric Double-Gate MOSFET for Low Power Circuit Simulation.
Period. Polytech. Electr. Eng. Comput. Sci., 2020

2017
Modeling of Threshold Voltage and Subthreshold Current for P-Channel Symmetric Double-Gate MOSFET in Nanoscale Regime.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2015
Implementation of high speed processor for computing convolution sum for DSP applications.
Proceedings of the 9th International Conference on Ubiquitous Information Management and Communication, 2015

Integer division technique for signal processing applications.
Proceedings of the 9th International Conference on Ubiquitous Information Management and Communication, 2015

2014
Design of 64-Bit Squarer Based on Vedic Mathematics.
J. Circuits Syst. Comput., 2014

Improved matrix multiplier design for high-speed digital signal processing applications.
IET Circuits Devices Syst., 2014

2013
Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

2012
Design of High Speed Vedic Multiplier for Decimal Number System.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

2011
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics.
Microelectron. J., 2011

Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications.
Proceedings of the International Symposium on Electronic System Design, 2011


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