Prabir Saha

According to our database, Prabir Saha authored at least 17 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Design of a Novel Inexact 4:2 Compressor and Its Placement in the Partial Product Array for Area, Delay, and Power-Efficient Approximate Multipliers.

Srikant Kumar Beura, Bishnulatpam Pushpa Devi, Prabir Saha, Pramod Kumar Meher

Circuits Syst. Signal Process., June, 2024

Inexact radix-4 Booth multipliers based on new partial product generation scheme for image multiplication.

Srikant Kumar Beura, Sudeshna Manjari Mahanta, Bishnulatpam Pushpa Devi, Prabir Saha

Integr., January, 2024

2022

Minimizing Ancilla Inputs and Garbage Outputs of Reversible BCD Multiplier.

Sheba Diamond Thabah, Prabir Saha

J. Circuits Syst. Comput., 2022

2021

Improved Signed Binary Multiplier Through New Partial Product Generation Scheme.

Sheba Diamond Thabah, Prabir Saha

J. Circuits Syst. Comput., 2021

Design and Analysis of Inexact 3: 2 Compressor-based Radix-4 Multiplier towards Image Multiplication.

Srikant Kumar Beura, Gudmalwar Ashishkumar Prabhakar, Sudesna Manjari Mahanta, Bishnulatpam Pushpa Devi, Prabir Saha

Proceedings of the 12th International Conference on Computing Communication and Networking Technologies, 2021

2020

New design approaches of reversible BCD encoder using Peres and Feynman gates.

Sheba Diamond Thabah, Prabir Saha

ICT Express, 2020

A Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder.

Sheba Diamond Thabah, Prabir Saha

Period. Polytech. Electr. Eng. Comput. Sci., 2020

Modeling of Short P-Channel Symmetric Double-Gate MOSFET for Low Power Circuit Simulation.

Rekib Uddin Ahmed, Prabir Saha

Period. Polytech. Electr. Eng. Comput. Sci., 2020

2017

Modeling of Threshold Voltage and Subthreshold Current for P-Channel Symmetric Double-Gate MOSFET in Nanoscale Regime.

Rekib Uddin Ahmed, Prabir Saha

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2015

Implementation of high speed processor for computing convolution sum for DSP applications.

Prabir Saha, Deepak Kumar, Abhijit Sharma

Proceedings of the 9th International Conference on Ubiquitous Information Management and Communication, 2015

Integer division technique for signal processing applications.

Deepak Kumar, Abhijit Sharma, Prabir Saha

Proceedings of the 9th International Conference on Ubiquitous Information Management and Communication, 2015

2014

Design of 64-Bit Squarer Based on Vedic Mathematics.

Prabir Saha, Deepak Kumar, Partha Bhattacharyya, Anup Dandapat

J. Circuits Syst. Comput., 2014

Improved matrix multiplier design for high-speed digital signal processing applications.

Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat

IET Circuits Devices Syst., 2014

2013

Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications.

Prabir Saha, Deepak Kumar, Partha Bhattacharyya, Anup Dandapat

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

2012

Design of High Speed Vedic Multiplier for Decimal Number System.

Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

2011

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics.

Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya

Microelectron. J., 2011

Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications.

Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat

Proceedings of the International Symposium on Electronic System Design, 2011