Prabhu Vellaisamy
Orcid: 0009-0007-7750-8725
According to our database1,
Prabhu Vellaisamy
authored at least 11 papers
between 2022 and 2024.
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Bibliography
2024
TNNGen: Automated Design of Neuromorphic Sensory Processing Units for Time-Series Clustering.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024
Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs.
CoRR, 2024
OzMAC: An Energy-Efficient Sparsity-Exploiting Multiply-Accumulate-Unit Design for DL Inference.
CoRR, 2024
Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference.
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Proceedings of the International Conference on Neuromorphic Systems, 2024
2023
tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
tuGEMM: Area-Power-Efficient Temporal Unary GEMM Architecture for Low-Precision Edge AI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
CoRR, 2022
TNN7: A Custom Macro Suite for Implementing Highly Optimized Designs of Neuromorphic TNNs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022