Prabhat Mishra
Orcid: 0000-0003-3653-6221Affiliations:
- University of Florida, Gainesville, USA
According to our database1,
Prabhat Mishra
authored at least 239 papers
between 2001 and 2024.
Collaborative distances:
Collaborative distances:
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on id.loc.gov
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on cise.ufl.edu
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Bibliography
2024
Revealing CNN Architectures via Side-Channel Analysis in Dataflow-based Inference Accelerators.
ACM Trans. Embed. Comput. Syst., November, 2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024
HIVE: Scalable Hardware-Firmware Co-Verification Using Scenario-Based Decomposition and Automated Hint Extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024
ACM Trans. Design Autom. Electr. Syst., May, 2024
ACM Comput. Surv., May, 2024
ACM Trans. Design Autom. Electr. Syst., March, 2024
Assertion-Based Validation using Clustering and Dynamic Refinement of Hardware Checkers.
ACM Trans. Design Autom. Electr. Syst., 2024
CISELeaks: Information Leakage Assessment of Cryptographic Instruction Set Extension Prototypes.
IACR Cryptol. ePrint Arch., 2024
CoRR, 2024
CoRR, 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
Verifying Memory Confidentiality and Integrity of Intel TDX Trusted Execution Environments.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024
EvilCS: An Evaluation of Information Leakage through Context Switching on Security Enclaves.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms.
IEEE Trans. Very Large Scale Integr. Syst., September, 2023
Efficient Detection and Localization of DoS Attacks in Heterogeneous Vehicular Networks.
IEEE Trans. Veh. Technol., May, 2023
ACM J. Emerg. Technol. Comput. Syst., January, 2023
Modeling and Exploration of Gain Competition Attacks in Optical Network-on-Chip Architectures.
CoRR, 2023
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
Digital Watermarking for Detecting Malicious Intellectual Property Cores in NoC Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE ACM Trans. Comput. Biol. Bioinform., 2022
Hardware-Assisted Malware Detection and Localization Using Explainable Machine Learning.
IEEE Trans. Computers, 2022
J. Hardw. Syst. Secur., 2022
IEEE Embed. Syst. Lett., 2022
Eavesdropping Attack Detection Using Machine Learning in Network-on-Chip Architectures.
IEEE Des. Test, 2022
ACM Comput. Surv., 2022
IEEE Access, 2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
Efficient Finite State Machine Encoding for Defending Against Laser Fault Injection Attacks.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Design of AI Trojans for Evading Machine Learning-based Detection of Hardware Trojans.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
ACM Trans. Design Autom. Electr. Syst., 2021
MaxSense: Side-channel Sensitivity Maximization for Trojan Detection Using Statistical Test Patterns.
ACM Trans. Design Autom. Electr. Syst., 2021
Scalable Activation of Rare Triggers in Hardware Trojans by Repeated Maximal Clique Sampling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
CoRR, 2021
CoRR, 2021
Denial-of-service attack detection using machine learning in network-on-chip architectures.
Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021
Accelerating Spectral Normalization for Enhancing Robustness of Deep Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Lightweight Encryption Using Chaffing and Winnowing with All-or-Nothing Transform for Network-on-Chip Architectures.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021
Automated Detection of Spectre and Meltdown Attacks Using Explainable Machine Learning.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Real-Time Detection and Localization of Denial-of-Service Attacks in Heterogeneous Vehicular Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Automated Test Generation for Hardware Trojan Detection using Reinforcement Learning.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
ACM Trans. Design Autom. Electr. Syst., 2020
IEEE Trans. Emerg. Top. Comput., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Special Session: Impact of Noise on Quantum Algorithms in Noisy Intermediate-Scale Quantum Systems.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Automated Test Generation for Trojan Detection using Delay-based Side Channel Analysis.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Guest Editorial: Special Section on Autonomous Intelligence for Security and Privacy Analytics.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
ACM Trans. Design Autom. Electr. Syst., 2019
Cache Reconfiguration Using Machine Learning for Vulnerability-aware Energy Optimization.
ACM Trans. Embed. Comput. Syst., 2019
Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Computers, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019
2018
IEEE Trans. Inf. Forensics Secur., 2018
J. Hardw. Syst. Secur., 2018
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018
Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution.
Proceedings of the IEEE International Test Conference, 2018
Proactive Thermal Management using Memory-based Computing in Multicore Architectures.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
ACM Trans. Embed. Comput. Syst., 2017
IEEE Des. Test, 2017
Vulnerability-Aware Energy Optimization Using Reconfigurable Caches in Multicore Systems.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Automated Debugging of Arithmetic Circuits Using Incremental Gröbner Basis Reduction.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
QUEBS: Qualifying Event Based Search in Concolic Testing for Validation of RTL Models.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Efficient Resource Constrained Scheduling Using Parallel Structure-Aware Pruning Techniques.
IEEE Trans. Computers, 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016
Exploiting transaction level models for observability-aware post-silicon test generation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, 2016
2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Variation-aware evaluation of MPSoC task allocation and scheduling strategies using statistical model checking.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
J. Electron. Test., 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Content-aware encoding for improving energy efficiency in multi-level cell resistive random access memory.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013
Branch-and-bound style resource constrained scheduling using efficient structure-aware pruning.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
2012
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012
System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2012
ACM Trans. Design Autom. Electr. Syst., 2012
ACM Trans. Embed. Comput. Syst., 2012
ACM Trans. Embed. Comput. Syst., 2012
TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Sustain. Comput. Informatics Syst., 2012
Sustain. Comput. Informatics Syst., 2012
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012
Memory-based computing for performance and energy improvement in multicore architectures.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Automated generation of directed tests for transition coverage in cache coherence protocols.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Computers, 2011
Sustain. Comput. Informatics Syst., 2011
J. Low Power Electron., 2011
IEEE Des. Test Comput., 2011
IEEE Des. Test Comput., 2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
A General Algorithm for Energy-Aware Dynamic Reconfiguration in Multitasking Systems.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
Efficient combination of trace and scan signals for post silicon validation and debug.
Proceedings of the 2011 IEEE International Test Conference, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Synergistic integration of dynamic cache reconfiguration and code compression in embedded systems.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems.
Proceedings of the 48th Design Automation Conference, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Functional Test Generation Using Efficient Property Clustering and Learning Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Des. Autom. Embed. Syst., 2010
Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme.
Proceedings of the 47th Design Automation Conference, 2010
2009
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation.
ACM Trans. Embed. Comput. Syst., 2009
ACM Trans. Embed. Comput. Syst., 2009
A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Guest Editor Introduction: Special Issue on Nano/Bio-Inspired Applications and Architectures.
Int. J. Parallel Program., 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the 46th Design Automation Conference, 2009
2008
Specification-driven directed test generation for validation of pipelined processors.
ACM Trans. Design Autom. Electr. Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
A novel test-data compression technique using application-aware bitmask and dictionary selection methods.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Specification-based compaction of directed tests for functional validation of pipelined processors.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008
2007
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007
An efficient code compression technique using application-aware bitmask and dictionary selection methods.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs.
ACM Trans. Design Autom. Electr. Syst., 2006
ACM Trans. Embed. Comput. Syst., 2006
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study.
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Test generation using SAT-based bounded model checking for validation of pipelined processors.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Functional test generation using property decompositions for validation of pipelined processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Int. J. Embed. Syst., 2005
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
Functional verification of programmable embedded architectures - a top-down approach.
Springer, ISBN: 978-0-387-26143-0, 2005
2004
ACM Trans. Embed. Comput. Syst., 2004
ACM Trans. Embed. Comput. Syst., 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004
Proceedings of the 2004 Design, 2004
2003
Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications.
Des. Autom. Embed. Syst., 2003
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation.
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003
2002
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions.
Proceedings of the Design and Analysis of Distributed Embedded Systems, IFIP 17<sup>th</sup> World Computer Congress, 2002
Automatic functional test program generation for pipelined processors using model checking.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002
Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units.
Proceedings of the 2002 Design, 2002
2001
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Functional abstraction driven design space exploration of heterogeneous programmable architectures.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001