Prab Varma

According to our database, Prab Varma authored at least 22 papers between 1984 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2016

Welcome Message.

Prab Varma, Miroslav N. Velev

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

2012

Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network Validation.

Prab Varma

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2004

Verification evolution or industrial revolution?

Prab Varma

IEEE Des. Test Comput., 2004

2003

Design Verification Problems: Test To The Rescue?

Prab Varma

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2001

ATPG for Design Errors-Is It Possible?

Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

2000

Test Cycle Count Reduction in a Parallel Scan BIST Environment.

Bechir Ayari, Prab Varma

J. Electron. Test., 2000

1998

A structured test re-use methodology for core-based system chips.

Prab Varma, Sandeep Bhatia

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

System chip test: are we there yet?

Prab Varma

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

System Chip Test Challenges, Are There Solutions Today? (Panel).

Prab Varma

Proceedings of the 35th Conference on Design Automation, 1998

1997

Test Compaction in a Parallel Access Scan Environment.

Sandeep Bhatia, Prab Varma

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

Delay Fault Testing: How Robust are Our Models?

Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

A Unifying Methodology for Intellectual Property and Custom Logic Testing.

Sandeep Bhatia, Tushar Gheewala, Prab Varma

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995

Optimizing Product Profitability - The Test Way.

Prab Varma

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994

The economics of scan-path design for testability.

Prab Varma, Tushar Gheewala

J. Electron. Test., 1994

On Path-Delay Testing in a Standard Scan Environment.

Prab Varma

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1993

Delay Testing Using a Matrix of Accessible Storage.

Prab Varma, Tushar Gheewala

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Scan DFT: Why More Can Cost Less.

Prab Varma

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1992

On test generation for path delay faults in ASICs.

Prab Varma

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1990

TDRC-a symbolic simulation based design for testability rules checker.

Prab Varma

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1988

A knowledge-based test generator for standard cell and iterative array logic circuits.

Prab Varma, Yoshihiro Tohma

IEEE J. Solid State Circuits, April, 1988

1987

A Fast Signature Simulation Tool for Built-In Self-Testing Circuits.

S. B. Tan, K. Totton, Keith Baker, Prab Varma, R. Porter

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1984

An Analysis of the Economics of Self Test.

Prab Varma, Anthony P. Ambler, Keith Baker

Proceedings of the Proceedings International Test Conference 1984, 1984