Pouya Hashemi

According to our database, Pouya Hashemi authored at least 3 papers between 2005 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

High-mobility high-Ge-content Si1-xGex-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x∼ 0.7, scaled EOT∼8.5Å and ∼10nm fin width.

Pouya Hashemi, Takashi Ando, Karthik Balakrishnan, John Bruley, Sebastian U. Engelmann, John A. Ott, Vijay Narayanan, D.-G. Park, Renee T. Mo, Effendi Leobandung

Proceedings of the Symposium on VLSI Circuits, 2015

2010

Gate-all-around silicon nanowire complementary metal-oxide-semiconductors: top-down fabrication and transport enhancement techniques.

Pouya Hashemi

PhD thesis, 2010

2005

The Influence of the Stacked and Double Material Gate Structures on the Short Channel Effects in SOI MOSFETS.

Ehsanollah Fathi, Ashkan Behnam, Pouya Hashemi, Behzad Esfandyarpour, Morteza Fathipour

IEICE Trans. Electron., 2005