Pouya Fotouhi

Orcid: 0000-0002-5891-4003

According to our database1, Pouya Fotouhi authored at least 15 papers between 2017 and 2022.

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Bibliography

2022
LLM: Realizing Low-Latency Memory by Exploiting Embedded Silicon Photonics for Irregular Workloads.
Proceedings of the High Performance Computing - 37th International Conference, 2022

2021
Scalable High Performance Memory Subsystem with Optical Interconnects
PhD thesis, 2021

HTA: A Scalable High-Throughput Accelerator for Irregular HPC Workloads.
Proceedings of the High Performance Computing - 36th International Conference, 2021

2020
Flex-LIONS: A Silicon Photonic Bandwidth-Reconfigurable Optical Switch Fabric.
IEICE Trans. Commun., 2020

The gem5 Simulator: Version 20.0+.
CoRR, 2020

Architecture and performance studies of 3D-Hyper-FleX-LION for reconfigurable all-to-all HPC networks.
Proceedings of the International Conference for High Performance Computing, 2020

2019
Enabling Scalable Disintegrated Computing Systems With AWGR-Based 25D Interconnection Networks.
JOCN, 2019

Flex-LIONS: A Scalable Silicon Photonic Bandwidth-Reconfigurable Optical Switch Fabric.
Proceedings of the 2019 24th OptoElectronics and Communications Conference (OECC) and 2019 International Conference on Photonics in Switching and Computing (PSC), 2019

3D photonics as enabling technology for deep 3D DRAM stacking.
Proceedings of the International Symposium on Memory Systems, 2019

Enabling scalable chiplet-based uniform memory architectures with silicon photonics.
Proceedings of the International Symposium on Memory Systems, 2019

2018
Experimental Demonstration of a 64-Port Wavelength Routing Thin-CLOS System for Data Center Switching Architectures.
JOCN, 2018

Towards Energy-Efficient High-Throughput Photonic NoCs for 2.5D Integrated Systems: A Case for AWGRs.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

AWGR-based optical processor-to-memory communication for low-latency, low-energy vault accesses.
Proceedings of the International Symposium on Memory Systems, 2018

2017
Leveraging access port positions to accelerate page table walk in DWM-based main memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Leveraging Compiler Optimizations to Reduce Runtime Fault Recovery Overhead.
Proceedings of the 54th Annual Design Automation Conference, 2017


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